Abstract: An array of circuit elements which when excited produces voltages is analyzed by examining successive voltage images produced by the circuit elements. Specifically, the array of circuit elements is repeatedly excited at high speed while the voltage image produced by the array is electro-optically sampled at a succession of clock times using a relatively slow-speed electro-optic image sampling technique using a burst clock, thereby to capture a succession of voltage images. The successive voltage images can be viewed on a display device directly individually, or they can be processed by an image processor which compares the successive voltage images with stored representations of voltage images to yield information regarding the condition of the array. Maximum permissible device operating speed can also be determined without examination of individual cells.

Abstract: An imaging method creates a two-dimensional image of a voltage distribution or a capacitance distribution of a substrate under test using an electro-optic modulator. A coarse modulator calibration determines the effect of non-uniformities in the modulator and determines a look-up table relating the gap distance between the modulator and the substrate to the intensity of the light emerging from the modulator. A positioning means calibration determines a look-up table relating control voltage to response by the positioning means. The modulator is moved over a portion of the substrate and then undergoes a positioning step, a fine onsite calibrating step, and a measuring step. The positioning step can be accomplished using the intensity of emerging light to determine modulator gap distance, and the response verses control voltage look-up table to determine a control signal to vertically position the modulator.

Abstract: A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects.

Abstract: A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects.

Abstract: LCD panels are inspected in-process to measure pixel decay, turn-on time and parasitic capacitance and/or identify pixel defects and line defects. Prior to final assembly, panels identified as having sufficiently few repairable defects are repaired. Line defects may be repaired. Further pixel defects may be repaired when redundant structures are included by splicing out the defective TFT or storage capacitor and splicing in a redundant, built-in TFT or storage capacitor. The inspection and repair systems are linked through a repair file. The inspection system identifies each defect by type and location and includes such information in the repair file. The repair system accesses such file and follows a prescribed repair method for a given type of defect at the location of such defect. The inspection system includes an automated non-contact voltage imaging system. The repair system includes lasers and means for repairing defects by adding metallization.

Abstract: An imaging method creates a two-dimensional image of a voltage distribution or a capacitance distribution across a surface of a substrate under test using an electro-optic modulator which is positioned and biased with respect to the surface of the substrate. The method involves a first coarse offsite calibrating step to compensate for nonuniformities in the light emerging from the modulator. Then, for each successive portion of the substrate over which the modulator is to detect characteristics of the substrate, the system undergoes a modulator relocating step, a modulator levelling step, a modulator gapping step, a fine onsite calibrating step, and a measuring step.

Abstract: An apparatus for testing a circuit board is provided employing a probe panel having a high density of photoelectrically addressable electrodes, each of the electrodes being coupled to a photoelectric switch connected to an outside source such as a voltage strip, and further employing photoelectric means for selectively activating each photoelectric switch as desired to apply test signals to selected locations of a circuit board. In one embodiment, a light panel having an array of pixels having a form factor scalably matching the electrode array is used to activate the photoelectric switches. A second embodiment uses a second probe panel on the circuit board side opposite the first probe panel. The desired light panel is a liquid crystal display panel using a laser diode as a light source.

Abstract: Circuit panels, such as LCD panels, are inspected in-process and after final assembly to identify defects. Prior to final assembly, panels identified as having sufficiently few defects are repaired. Similarly after final assembly, panels identified as having sufficiently few defects are repaired. The inspection and repair systems are linked through a repair file. The inspection system identifies each defect by type and location and includes such information in the repair file. The repair system accesses such file and follows a prescribed repair method for a given type of defect at the location of such defect. Simple matrix panel defects include open line defects and line to line shorts. The inspection system includes an automated non-contact capacitance imaging system. The repair system may include a pair of lasers and a film dispenser. A first laser is used to selectively remove material and cut lines. The dispenser is for applying a liquid organic metallic film in the defect area.

Abstract: An unassembled simple matrix liquid crystal display (LCD) panel, with strips of highly-conductive material, is tested by extracting a two-dimensional image of the capacitance distribution across the surface of the panel under test (PUT) through illumination of a modulator placed adjacent the surface, such as an NCAP modulator or other liquid dispersed polymer-based device. The light modulator is disposed to allow longitudinal probing geometries such that a measurement of capacitance is developed across a gap between the surface of the panel under test and the opposing face of the modulator which causes a power modulation in the optical energy which can be observed through an area optical sensor (such as a camera) for use in directly produce a two-dimensional spatially-dependent power modulation image directly representative of the spatially corresponding capacitance state on the surface of the panel under test.

Abstract: A laser-based repair system provides for material removal and deposition using a repair tool having a first laser operating at a high power for cutting signal lines and operating at a lower power for ablating a target repair area in conjunction with a liquid dispensing apparatus for application of the liquid solution in a target area, and a second laser for decomposing the liquid solution in an applied layer prior to the ablation of material in the target repair area. Various repair processes can be undertaken. The invention allows high-speed material deposition and removal on a surface. In a specific embodiment of the invention, the liquid solution used is a palladium acetate and a solvent or other metallo-organic solution which is capable of pyrolytic reaction and decomposition to an electrically conductive residue. A liquid applicator or dispensing apparatus is provided which is suited to applying fine traces of liquid without clogging.

Abstract: A method and apparatus for measuring an electro-optic voltage signal generated in response to an applied voltage signal at a select dot contact of an electro-optic crystal. The applied voltage signal is time averaged along one path to generate an average reference voltage signal, and electro-optically measured along another path to provide a corresponding electro-optic voltage signal. The electro-optic system is fine offset calibrated during a run, with the electro-optic voltage signal measured after the calibration. During the fine offset calibration, the electro-optic voltage signal and the average reference voltage signal are input to an integrator generating a responsive offset signal. The timing correlation between the applied voltage signal the electro-optic voltage signal is randomized during this calibration so that the generated electro-optic voltage signal is an average. The feedback forces the electro-optic signal to the average reference voltage signal level.

Abstract: A two-dimensional image of the voltage distribution across a surface at a large plurality voltage test points of a panel under test is extracted by illuminating the surface with an input beam of optical energy through an electro-optic modulator wherein the modulator is disposed to allow longitudinal probing geometries such that a voltage differential on the surface of the panel under test causes a power modulation in the optical energy which can be observed through an area optical sensor (a camera) for use to directly produce a two-dimensional spatially-dependent power modulation image directly representative of the spatially corresponding differential voltage state on the surface of the panel under test. Surface cross-talk is minimized by placing the face of the modulator closer to the panel under test than the spacing of voltage sites in the panel under test. The device may operate in a pass-through mode or in a reflective mode.

Abstract: A two-dimensional image of the voltage distribution across a surface at a large plurality voltage test points of a panel under test is extracted by illuminating the surface with an input beam of optical energy through an electro-optic modulator wherein the modulator is disposed to allow longitudinal probing geometries such that a voltage on the surface of the panel under test causes a power modulation in the optical energy which can be observed through an area optical sensor (a camera) for use to directly produce a two-dimensional spatially-dependent power modulation image directly representative of the spatially corresponding voltage state on the surface of the panel under test. Surface crosstalk is minimized by placing the face of the modulator closer to the panel under test than the spacing of voltage sites in the panel under test. The device may operate in a passthrough mode or in a reflective mode.

Abstract: A high-speed electro-optic test system for testing high-speed electronic devices and integrated circuits is provided with a precision programmable reference clock source providing clock pulses for accurately timing a stimulus pattern in precise synchronism with optical sampling pulses. The clock source includes a frequency synthesizer having a programmed output frequency and precision delay features. The stimulus pattern clock frequency and pattern length can be programmed to facilitate maximum throughput for devices being tested in the electro-optic system.

Abstract: Final testing of an LCD panel or the like is performed after preliminary testing for short circuit defects. During final testing, the panel is exposed to signals at the shorting bars and the resulting display pattern is imaged. The resulting image data then is processed at a computer system to determine whether the resulting display pattern differs from an expected display pattern. If differences are present then an open circuit or pixel defect is present. The applied test signals and the pattern or differences determine the type of defect present. For an open circuit defect along a gate line, a partial row (column) of the resulting display pattern does not activate. For an open circuit along a drive line, a partial column (row) of the resulting display does not activate. Pixel shorts are identified by applying test signals to the shorting bars during a first test cycle, then imaging the display during a second test cycle after at least one of the test signals is removed.

Abstract: An LCD panel or the like is tested by determining whether any short circuit defects are present. The panel is tested for short circuit defects by scanning gate lines and drive lines with a magnetic field pickup device while a current is applied to a shorting bar which shorts together a plurality of gate lines or a plurality of drive lines. When a short circuit defect is present, a current flows through the shorted area. As a result, a corresponding magnetic field is generated along the involved lines. For a cross-short defect, the location of the defect is identified as the intersection of the drive line and gate line which generate magnetic fields of substantially the same strength.

Abstract: A two-dimensional image of the voltage distribution across a surface at a large plurality voltage test points of a panel under test is extracted by illuminating the surface with an expanded, collimated beam of optical energy of a known polarization state through an electro-optic modulator crystal, such as KDP, wherin the crystal is disposed to allow longitudinal probing geometries such that a voltage on the surface of the panel under test causes a phase shift in the optical energy (the electro-optic effect) which can be observed through an area polarization sensor (a polarizing lens) for use to directly produce a two-dimensional spatially-dependent power modulation image directly representative of the spatially corresponding voltage state on the surface of the panel under test. Surface cross-talk is minimized by placing the face of the crystal closer to the panel under test than the spacing of voltage sites in the panel under test. The device may operate in a pass-through mode or in a reflective mode.

Abstract: A high speed test system for performing tests on various electrical devices including integrated circuits and semiconductor wafers at device operating speeds in the Gigahertz range. The test system including a test head having a test platform for receiving an adapter board that holds the device under test. The test platform is exposed on one side of the test head to facilitate readily changing the tested devices and easy coupling with conventional wafer prober machines. A plurality of pin driver boards are positioned radially about the test platform to minimize the distance between the device under test and the pin driver boards. Electrical signals presented at specific locations on the device under test are measured in response to the inputted signals form the pin drivers using an electro-optic sensor preferably located central of the pin driver boards and within 1.0 cm of the device under test to minimize pin capacitance.

Abstract: The conductive state of a transistor in a semiconductor integrated circuit is determined by irradiating the transistor with a radiation beam and measuring changes in load current, thereby indicating whether the transistor was conducting or non-conducting prior to irradiation. A correlated double sampling method is employed in measuring changes in load current. A load resistor in series with the device under test is capacitively coupled to a differential amplification means including a plurality of differential amplifiers with buffers connected between successive amplifiers. A system clock is stopped at a predetermined time period prior to irradiating the transistor. A bypass switch shunts the load resistor until the clock is stopped.