Abstract: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

Abstract: In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base.

Abstract: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

Abstract: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.

Abstract: A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.

Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.

Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.

Abstract: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.

Abstract: The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.

Abstract: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.

Abstract: A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.

Abstract: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

Abstract: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.