Abstract: The invention relates to a method for solid-phase microextraction and analysis of substances in a carrier fluid, in which a collector is brought into contact with the stirred fluid containing the substances for a sufficient time and is then subjected to a solid-phase extraction directed at at least one substance adhering to the collector, and desorbed substances are transported for analysis by means of a carrier gas, in which the carrier fluid containing the substances is stirred in a receptacle of a magnetic stirrer by means of a coated magnetic stirring element as the collector, and/or the carrier fluid is made to move intimately relative to the collector by means of ultrasound, and then the stirring element is placed in a solid-phase extraction device.

Abstract: The invention relates to a method for solid-phase microextraction and analysis of substances in a carrier fluid, in which a collector is brought into contact with the stirred fluid containing the substances for a sufficient time and is then subjected to a solid-phase extraction directed at at least one substance adhering to the collector, and desorbed substances are transported for analysis by means of a carrier gas, in which the carrier fluid containing the substances is stirred in a receptacle of a magnetic stirrer by means of a coated magnetic stirring element as the collector, and/or the carrier fluid is made to move intimately relative to the collector by means of ultrasound, and then the stirring element is placed in a solid-phase extraction device.

Abstract: Drives of a data storage library are concurrently configured. A processor transmits library configuration data separately to each drive, initializes a first configuration process state, with a time-out period, for each drive. A drive responds with a status response, the first process state is updated to “completed”. A request for drive unique information is transmitted to the responding drive, advancing the process to a second state, with a time-out period. A drive responds with the information, and the second process state is updated to “completed”, and the received information is stored.

Abstract: A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bits. The failed bit indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

Abstract: An electroconductive coating composition which function as a sealer/primer includes (a) a radiation curable, polymerizable compound, (b) a photoinitiator and (c) a conductive pigment. The conductive pigment may be a mixture of pigment including a blend of conductive pigments as well as conductive pigment. Conductivity enhancers may, also, be added. The polymerizable compound is, preferably, a U curable acrylate functional compound which may be monofunctional or polyfunctional. The composition is particularly useful for sealing and priming SMC panels.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: A system, a method, and a computer program product to provide a failover procedure for an automated data storage library are provided. During the operation of a data storage library, a host computer issues control commands to the automated data storage library using one or more control paths. In the event that the host does not receive desirable results, such as when communication is lost between the host computer and the automated data storage library while a command is in process, the host computer may attempt to retry the same command using the same control path or an alternate control path. When the host issues a retry of the same command, the automated data storage library performs an examination of the command and one or more previous commands executed to prevent the automated data storage library from executing an identical command more than once.

Abstract: Provided is a method, system, and program for providing status information in a system comprised of multiple components. A first processing node receives status information indicating a state of a system component and generates a status message indicating the state of the system component. The first processing node transmits the status message to a second processing node. The second processing node updates information maintained by the second processing node with the state of the system component indicated in the status message. Status information maintained by the second processing node is returned to a request for status.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: A comparator and method for detecting a signal using a reference derived from a differential data signal pair improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel comparator circuit provides the comparison, using a voltage or current level of the single-ended signal to determine states of the differential data signal pair.

Abstract: A portable data storage drive cartridge has external interfaces positioned respectively at opposite ends of a cartridge shell. They may be arranged to be similar when the cartridge is rotated end over end to a reverse direction with respect to the opposite ends. A data storage drive, such as a magnetic disk drive assembly, having an interface, is positioned in the cartridge shell with the drive interface positioned toward a first end and away from a second end of the opposite ends of the cartridge shell. Flex cables extend from the drive interface, a first extending from the drive interface around the drive to the external interface at the second end of the cartridge shell, and a second extending from the drive interface, initially around the drive toward the second end, and reversing direction and extending back to the external interface at the first end of the cartridge shell.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Abstract: A method to return an automated data storage and retrieval system from a reset state to the ready state. An automated data storage and retrieval system which includes a computer useable medium having computer readable program code disposed therein to implement Applicants' method to return the automated data storage and retrieval system to the ready state from a reset state. A method to allocate storage elements disposed within an automated data storage and retrieval system while that automated data storage and retrieval system is in a reset state. An automated data storage and retrieval system which includes computer readable program code disposed therein to implement Applicants' method to allocate storage elements disposed within an automated data storage and retrieval system while that automated data storage and retrieval system is in a reset state. A method to adjust the system recovery period of an automated data storage and retrieval system after that system is placed in a reset state.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (“Bus clock”) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (“Local clock”) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master.

Abstract: Drives of a data storage library are concurrently configured. A processor transmits library configuration data separately to each drive, initializes a first configuration process state, with a time-out period, for each drive. A drive responds with a status response, the first process state is updated to “completed”. A request for drive unique information is transmitted to the responding drive, advancing the process to a second state, with a time-out period. A drive responds with the information, and the second process state is updated to “completed”, and the received information is stored.

Abstract: A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.