Patents by Inventor Frank Greer

Frank Greer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319868
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: June 11, 2019
    Assignee: NANOCLEAR TECHNOLOGIES INC.
    Inventors: Harold Frank Greer, Rehan Rashid Kapadia, Ryan Morrow Briggs
  • Publication number: 20190074389
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Application
    Filed: October 3, 2018
    Publication date: March 7, 2019
    Inventors: Harold Frank GREER, Scott S. HARRIED, Ryan Morrow BRIGGS, Tony LEE
  • Publication number: 20190016593
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 17, 2019
    Inventors: Harold Frank GREER, Ryan Morrow BRIGGS
  • Publication number: 20180363277
    Abstract: An atmospheric water generation system with high efficiency is based on a counter flowing heat exchanger including multiple cold channels, each cold channel surrounded by multiple hot channels. The hot and warm gases flow in opposite directions, allowing the cool dry air to contribute to cooling the warm humid air to the dew point. Thermoelectric or passive cooling of the warm humid air, and hydrophobic surfaces in a cyclone structure also contribute in increasing the efficiency of the water generation system.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 20, 2018
    Inventors: Harold Frank GREER, Peter CAPAK, Aria ANVAR
  • Patent number: 10121919
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 6, 2018
    Assignee: NANOCLEAR TECHNOLOGIES INC.
    Inventors: Harold Frank Greer, Scott S. Harried, Ryan Morrow Briggs, Tony Lee
  • Publication number: 20180201395
    Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.
    Type: Application
    Filed: July 15, 2015
    Publication date: July 19, 2018
    Applicant: California Institute of Technology
    Inventors: Cecile Jung-Kubiak, Colleen M. Marrese-Reading, Victor E. White, Daniel W. Wilson, Matthew R. Dickie, Karl Y. Yee, Richard E. Muller, James E. Polk, John R. Anderson, Nima Rouhi, Frank Greer
  • Publication number: 20180194619
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Application
    Filed: August 3, 2017
    Publication date: July 12, 2018
    Inventors: Harold Frank GREER, Ryan Morrow BRIGGS
  • Publication number: 20180198003
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Application
    Filed: August 3, 2017
    Publication date: July 12, 2018
    Inventors: Harold Frank GREER, Rehan Rashid KAPADIA, Ryan Morrow BRIGGS
  • Publication number: 20180198006
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Application
    Filed: August 3, 2017
    Publication date: July 12, 2018
    Inventors: Harold Frank GREER, Scott S. HARRIED, Ryan Morrow BRIGGS, Tony LEE
  • Patent number: 10017384
    Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: July 10, 2018
    Assignee: NANOCLEAR TECHNOLOGIES INC.
    Inventors: Harold Frank Greer, Ryan Morrow Briggs
  • Publication number: 20170186935
    Abstract: Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Joseph Anthony Bonetti, Frank Greer, Wenxian Zhu
  • Patent number: 9455393
    Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 27, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Ashish Bodke, Frank Greer, Mark Clark
  • Patent number: 9425376
    Abstract: In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 23, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Andy Steinbach
  • Patent number: 9373497
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 21, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Haruhiro Harry Goto, Martina Su, Frank Greer, Shamsuddin Alokozai
  • Publication number: 20160133819
    Abstract: Provided are superconducting circuits and methods of forming such circuits. A circuit may include a silicon containing low loss dielectric (LLD) layer formed by fluorine passivation of dangling bonds of silicon atoms in the layer. The LLD layer may be formed from silicon nitride or silicon oxide. For uniform passivation (e.g., uniform distribution of fluorine within the LLD layer), fluorine may be introduced while forming the LLD layer. For example, a fluorine containing precursor may be supplied into a deposition chamber together with a silicon containing precursor. Alternatively, the LLD layer may be formed as a stack of many thin sublayers, and each sublayer may be subjected to individual fluorine passivation. For example, low power plasma treatment or annealing in a fluorine containing environment may be used for this purpose. The concentration of fluorine in the LLD layer may be between about 0.5% atomic and 5% atomic.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicant: Intermolecular, Inc.
    Inventors: Frank Greer, Ashish Bodke
  • Patent number: 9324767
    Abstract: Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: April 26, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Andrew Steinbach, Tony Bonetti, Frank Greer, Kurt Pang, Yun Wang
  • Patent number: 9312137
    Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 12, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
  • Publication number: 20160093772
    Abstract: Provided are methods of forming low resistivity contacts. Also provided are devices having such low resistive contacts. A method may include doping the surface of a structure, such as a gallium nitride layer. Specifically, a dopant containing layer is formed on the surface of the structure using, for example, atomic layer deposition (ALD). The dopant may magnesium. In some embodiments, the dopant containing layer also includes nitrogen. A capping layer may be then formed over the dopant containing layer to prevent dopant desorption. The stack including the structure with the dopant containing layer disposed on its surface is then annealed to transfer dopant from the dopant containing layer into the surface. After annealing, any remaining dopant containing layer is removed. When another component is later formed over the surface, a low resistivity contact is created between this other component and the doped structure.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Khaled Ahmed, Frank Greer, Andrew Steinbach
  • Patent number: 9281463
    Abstract: Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 8, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Andy Steinbach
  • Patent number: 9245793
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 26, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Frank Greer, Chi-I Lang, J. Watanabe, Wenxian Zhu