Patents by Inventor Frank Hellwig
Frank Hellwig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10248595Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.Type: GrantFiled: August 10, 2017Date of Patent: April 2, 2019Assignee: Infineon Technologies AGInventors: Frank Hellwig, Gerhard Wirrer, Glenn Farrall, Neil Hastie
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Publication number: 20190065787Abstract: The present disclosure relates to a security device, a system, and a method for securing a control apparatus. The security device includes a data security unit which is configured to secure data, data communication and information, and includes a first security component inside the data security unit to operate in a first operating mode, and at least one first monitoring unit to operate in a high-availability mode which, said first monitoring unit being configured to detect a fault present in the first security component. The high-availability mode is different from the first operating mode. The security device further includes a second security component which is configured to operate in the high-availability mode and to output a first response signal if a fault is detected by the first monitoring, where the high-availability mode is available independently from the first operating mode.Type: ApplicationFiled: August 22, 2018Publication date: February 28, 2019Applicant: Infineon Technologies AGInventors: Avni BILDHAIYA, Viola RIEGER, Frank HELLWIG, Alexander ZEH
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Publication number: 20190050356Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Frank Hellwig, Gerhard Wirrer, Glenn Farrall, Neil Hastie
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Patent number: 10061729Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.Type: GrantFiled: March 19, 2018Date of Patent: August 28, 2018Assignee: Ifineon Technologies AGInventors: Albrecht Mayer, Joerg Schepers, Frank Hellwig
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Publication number: 20180210852Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.Type: ApplicationFiled: March 19, 2018Publication date: July 26, 2018Inventors: Albrecht Mayer, Joerg Schepers, Frank Hellwig
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Publication number: 20180113816Abstract: A memory protector is configured to evaluate access requests referring to a memory address space. The access requests comprise address parameters referring to addresses of the memory address space. The memory protector comprises an address evaluator, an address results combiner, and a data register. The address evaluator is configured to evaluate whether the address parameters refer to address ranges of a set of address ranges and is configured to provide results regarding the address ranges. The address results combiner is configured to combine results provided by the address evaluator depending on access protection groups to which the address ranges are mapped to. The memory protector is configured to provide access grant results based on combinations provided by the address results combiner. The data register is configured to store data concerning the set of address ranges and concerning a mapping of the address ranges to the access protection groups.Type: ApplicationFiled: October 16, 2017Publication date: April 26, 2018Inventors: Frank Hellwig, Glenn Ashley Farrall, Gerhard Wirrer
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Patent number: 9946674Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.Type: GrantFiled: April 28, 2016Date of Patent: April 17, 2018Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Joerg Schepers, Frank Hellwig
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Publication number: 20180039508Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Inventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 9836318Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: GrantFiled: March 12, 2014Date of Patent: December 5, 2017Assignee: Infineon Technologies AGInventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Publication number: 20170315944Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Albrecht Mayer, Joerg Schepers, Frank Hellwig
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Publication number: 20170302441Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.Type: ApplicationFiled: April 13, 2017Publication date: October 19, 2017Inventors: Christopher Temple, Simon Cottam, Frank Hellwig, Antonio Vilela
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Patent number: 9703728Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.Type: GrantFiled: September 23, 2014Date of Patent: July 11, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam
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Patent number: 9575912Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.Type: GrantFiled: April 8, 2014Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam, Krishnapriya Chakiat Ramamoorthy
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Patent number: 9569384Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.Type: GrantFiled: March 14, 2013Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam, Harald Zweck
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Patent number: 9181006Abstract: A can for containing a liquid has a top end. The top end has a dispense area defined on the top end by a first score line and a vent area defined on the top end by a second score line separate from the first score line. The top end has a first rivet located between the vent and dispense areas for coupling to the top end. The top end has a pull tab suitable for puncturing the dispense areas to open a dispense aperture. The top end has a device for opening the vent aperture. The dispense area has a dimension along the diameter of the top end passing by the first rivet greater or equal to the radius of the top end.Type: GrantFiled: December 21, 2012Date of Patent: November 10, 2015Assignee: Anheuser-Busch InBev S.A.Inventors: Christopher Neiner, Frank Hellwig
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Publication number: 20150286596Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: Infineon Technologies AGInventors: Frank HELLWIG, Simon COTTAM, Krishnapriya Chakiat RAMAMOORTHY
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Publication number: 20150242233Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: ApplicationFiled: March 12, 2014Publication date: August 27, 2015Inventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 8996926Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.Type: GrantFiled: October 15, 2012Date of Patent: March 31, 2015Assignee: Infineon Technologies AGInventors: Simon Brewerton, Simon Cottam, Frank Hellwig
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Publication number: 20150089175Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.Type: ApplicationFiled: September 23, 2014Publication date: March 26, 2015Inventors: Frank Hellwig, Simon Cottam
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Publication number: 20140367382Abstract: A can for containing a liquid having a top end is disclosed. The top end has a dispense area defined on the top end by a first score line and a vent area defined on the top end by a second score line separate from the first score line. The top end has a first rivet located between the vent and dispense areas for coupling to the top end. The top end has a pull tab suitable for puncturing the dispense areas to open a dispense aperture. The top end has a device for opening the vent aperture. The dispense area has a dimension along the diameter of the top end passing by the first rivet greater or equal to the radius of the top end.Type: ApplicationFiled: December 21, 2012Publication date: December 18, 2014Inventors: Christopher Neiner, Frank Hellwig