Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: An apparatus for profiling a computer system, where the apparatus contains a resolution register, a counter, and a monitor. The resolution register stores a variable, which sets the timing for when the apparatus will create an output that can be used to gauge the system's performance. The counter counts the operations of the system, while the monitor monitors occurrences, activities that occur during each operation. Once the number of operations lapse equal to the variable, a reading is output.

Abstract: A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least one master device to use the bus system to access a slave device are received, and the priority values of all requesting master devices are compared. If a sole requesting master device has the highest priority value access to the respective slave device is granted to that master device. If a plurality of requesting master devices have the same highest priority value access is successively granted to the requesting master devices having the same highest priority value on the basis of the address allocation of the master devices.

Abstract: A configuration and method for operating the configuration includes first and second devices connected to one another through a cross bar and accessing one another through the cross bar for reading and/or writing data. When a read access to the second device occurs, the first device reads the data emitted from the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar, and, when a write access occurs from the first device to the second device, the first device emits the data to be written to the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar and the second device reads the data emitted from the first device when it receives a data valid signal produced by the first device and supplied to the second device through the cross bar.

Abstract: The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.

Abstract: A method for allocating bus access rights in a multimaster bus system (2), having the following steps: addresses (MASTER0-MASTER 15) are explicitly allocated to master devices (3-1, . . . 3-N) in the multimaster bus system, a priority value (P0, . . . P15) from an organized priority list (5) of priority values (P0 . . . P15) is assigned to each master device (3-1, . . . 3-N) provided in the multimaster bus system (2), requests from at least one master device (3-1, . . . 3-N) to use the bus system (2) to access a slave device (4-1, . . . 4-M) are received, the priority values (P0, . . . P15) of all requesting master devices (3-1, . . . 3-N) are compared, if a sole requesting master device (3-1, . . . 3-N) has the highest priority value (P0, . . . P15): sole access to the respective slave device (4-1, . . . 4-M) is granted to the requesting master device (3-1, . . . 3-N) which has the highest priority value (P0, . . . P15), or if a plurality of requesting master devices (3-1, . . .

Abstract: An arrangement comprises a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device. The memory device is supplied with a first clock signal and transmits the data at the rate of a second clock signal, and the second clock signal to the memory interface when the memory interface performs a read access. The first clock signal is also supplied to the memory interface which generates from this signal a third clock signal which has the same frequency as the first and second clock signal but a predetermined phase shift with respect to the second clock signal. The memory interface accepts the data with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.

Abstract: Method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit A description is given of a method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit. The method described is distinguished by the fact that identical items of individual information about processes of the same type are combined to form a single item of overall information. As a result, the desired information about the processes of interest can be procured with considerably less expenditure than was the case hitherto.

Abstract: The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.

Abstract: A configuration and method for operating the configuration includes first and second devices connected to one another through a cross bar and accessing one another through the cross bar for reading and/or writing data. When a read access to the second device occurs, the first device reads the data emitted from the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar, and, when a write access occurs from the first device to the second device, the first device emits the data to be written to the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar and the second device reads the data emitted from the first device when it receives a data valid signal produced by the first device and supplied to the second device through the cross bar.