Abstract: A PVD chamber for growing a magnetic film of NiFe alloy at a growth rate of greater than 200 nm/minute produces a film exhibiting magnetic skew of less than plus or minus 2 degrees, magnetic dispersion of less than plus or minus 2 degrees, DR/R of greater than 2 percent and film stress of less than 50 MPa. NiFe alloy is sputtered at a distance of 2 to 4 inches, DC power of 50 Watts to 9 kiloWats and pressure of 3 to 8 milliTorr. The chamber uses a unique field shaping magnetron having magnets arranged in outer and inner rings extending about a periphery of the magnetron except in two radially opposed regions in which the inner and outer rings diverge substantially toward a central axis of the magnetron.

Abstract: A thin film of material on a substrate is formed in a continuous process of a physical vapor deposition system, in which material is deposited during a variable temperature growth stage having a first phase conducted below a temperature of about 500° C., and material is continuously deposited as the temperature changes for the second phase to above about 800° C.

Abstract: A PVD chamber for growing a magnetic film of NiFe alloy at a growth rate of greater than 200 nm/minute produces a film exhibiting magnetic skew of less than plus or minus 2 degrees, magnetic dispersion of less than plus or minus 2 degrees, DR/R of greater than 2 percent and film stress of less than 50 MPa. NiFe alloy is sputtered at a distance of 2 to 4 inches, DC power of 50 Watts to 9 kiloWats and pressure of 3 to 8 milliTorr. The chamber uses a unique field shaping magnetron having magnets arranged in outer and inner rings extending about a periphery of the magnetron except in two radially opposed regions in which the inner and outer rings diverge substantially toward a central axis of the magnetron.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.

Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.

Abstract: A plasma enhanced atomic layer deposition (PEALD) method and system, the system including a process chamber and a substrate holder provided within the processing chamber and configured to support a substrate on which a predetermined film will be formed. A first process material supply system is configured to supply a first process material to the process chamber, and a second process material supply system configured to supply a second process material to the process chamber in order to provide a reduction reaction with the first process material to form the predetermined film on the substrate. Also included is a power source configured to couple electromagnetic power to the process chamber to generate a plasma within the process chamber to facilitate the reduction reaction, and a chamber component exposed to the plasma and made from a film compatible material that is compatible with the predetermined film deposited on the substrate.

Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.

Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.

Abstract: According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.

Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.

Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.

Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.

Abstract: Methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments, the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.

Abstract: A method light enhanced atomic layer deposition for forming a film on a substrate. The method includes disposing the substrate in a process chamber of a light enhanced atomic layer deposition (LEALD) system configured to perform a LEALD process; and depositing a film on the substrate using the LEALD process, where the depositing includes (a) exposing the substrate to a first process material, (b) exposing the substrate to a second process material containing a reducing agent and irradiating the substrate with a first light radiation having either no or at least partial temporal overlap with the exposing of the substrate to the second process material, (c) repeating steps (a) and (b) until the desired film has been deposited. According to one embodiment of the invention, the deposited film can be a TaCN film or a TaC film.

Abstract: An iPVD system uses a high density inductively coupled plasma (ICP) at high pressure of at least 50 mTorr to deposit uniform ultra-thin layer of a tantalum nitride material barrier material onto the sidewalls of high aspect ratio nano-size features on semiconductor substrates, preferably less than 2 nm thick with less than 4 nm in the field areas. The process includes depositing an ultra-thin TaN barrier layer having a high nitrogen concentration that produces high resistivity, preferably at least 1000 micro-ohm-cm. The ultra-thin TaN film is deposited by a low deposition rate process of less than 20 nm/minute, preferably 2-10 nm/min, to produce the high N/Ta ratio layer without nitriding the tantalum target. The layer provides a barrier to copper (Cu) diffusion and a high etch resistant etch-stop layer for subsequent deposition-etch processes.

Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Sequential deposition and etching are provided by controlling DC and high density power levels and other parameters.