Patents by Inventor Frank M. Cerio

Frank M. Cerio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100081274
    Abstract: A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NHx (x?3) radicals and H radicals to improve selective formation of ruthenium (Ru) metal cap layers on the metal layers relative to the low-k dielectric materials.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno, Frank M. Cerio, JR.
  • Publication number: 20100029078
    Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.
    Type: Application
    Filed: February 11, 2009
    Publication date: February 4, 2010
    Applicant: TEL EPION INC.
    Inventors: Noel Russell, Frank M. Cerio, JR., Gregory Herdt
  • Publication number: 20100029071
    Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: TEL EPION INC.
    Inventors: Noel Russell, Frank M. Cerio, JR., Gregory Herdt
  • Patent number: 7651568
    Abstract: A plasma enhanced atomic layer deposition (PEALD) system includes a first chamber component coupled to a second chamber component to provide a processing chamber defining an isolated processing space within the processing chamber. A substrate holder is provided within the processing chamber and configured to support a substrate, a first process material supply system is configured to supply a first process material to the processing chamber and a second process material supply system is configured to supply a second process material to the processing chamber. A power source is configured to couple electromagnetic power to the processing chamber, and a sealing assembly interposed between the first and second chamber components.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: January 26, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Tsukasa Matsuda, Frank M. Cerio, Jr., Kaoru Yamamoto
  • Publication number: 20100015798
    Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Kenji Suzuki, Frank M. Cerio, JR., Miho Jomen, Shigeru Mizuno, Yasushi Mizusawa, Tadahiro Ishizaka
  • Patent number: 7642201
    Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 5, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Frank M. Cerio, Jr., Shigeru Mizuno, Tsukasa Matsuda, Adam Selsey
  • Publication number: 20090321247
    Abstract: A method is provided of operating a deposition system to deposit coating material into high aspect ratio nano-sized features on a patterned substrate that enhances sidewall coverage compared to field area and bottom surface coverage while minimizing or eliminating overhang. The method includes performing a process step with a gross field area deposition rate of about 25 to 70 nm/min and simultaneously etching the barrier layer to establish a net field area deposition rate of about 5 to 40 nm/min. The method may also include first performing a protective layer deposition step with a field area deposition rate of about 5 to 20 nm/min without etching the underlying surface then performing a surface modification step with gross deposition and simultaneous etching at a field modification net deposition rate of about ?10 to +40 nm/min.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 31, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Frank M. Cerio, JR., Jacques Faguet, Bruce D. Gittleman, Rodney L. Robison
  • Patent number: 7618888
    Abstract: A method for performing ionized physical vapor deposition (iPVD) is described, whereby the substrate temperature can be rapidly changed to control a metal deposition process and increase the quality of the metal deposited. In one embodiment, a copper deposition process can be performed.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 17, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.
  • Publication number: 20090242385
    Abstract: A method for depositing a metal-containing film on a substrate using an inductively coupled (ICP) physical vapor deposition (PVD) system. The ICP PVD deposition is performed under process conditions that thermalize neutral sputtered metal atoms by collisions with a process gas and minimize or eliminate exposure of ions to the substrate.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Rodney L. Robison, Frank M. Cerio, JR.
  • Patent number: 7588667
    Abstract: An iPVD system is programmed to deposit a barrier and/or seed layer using a Ru-containing material into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within an IPVD processing chamber. In the preferred embodiment, an IPVD apparatus having a frusto-conical ruthenium target equipped with a high density ICP source is provided.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 15, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.
  • Publication number: 20090191721
    Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 30, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Frank M. Cerio, JR., Shigeru Mizuno, Tsukasa Matsuda, Adam Selsey
  • Patent number: 7348266
    Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Plural sequential dry filling plasma processes are used with backside gas pressure varied to control substrate temperature.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 25, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.
  • Patent number: 6268284
    Abstract: A method to deposit a composite metal to form a continuous, smooth film in high aspect ratio features such as vias, contacts and/or trenches on a wafer in a single step. Metal atoms are sputtered from a composite target containing a first metal and a second metal in a single reaction chamber. A physical vapor deposition processes such as ionized physical vapor deposition (IPVD) is preferred. In one embodiment, the first metal is titanium and the second metal is aluminum. The method eliminates a high temperature anneal and results in lower resistivity, a better wetting layer for subsequent deposition and improved control over thickness of the metal layer.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: July 31, 2001
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.