Patents by Inventor Frank O'Bleness
Frank O'Bleness has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8806181Abstract: According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the data and instructions when the first processor pipeline is selected; a second processor pipeline configured to process the data and instructions when the second processor pipeline is selected; and a selection module configured to select either the first processor pipeline or the second processor pipeline.Type: GrantFiled: May 1, 2009Date of Patent: August 12, 2014Assignee: Marvell International Ltd.Inventors: R. Frank O'Bleness, Sujat Jamil, Timothy S. Beatty, Franco Ricci, Tom Hameenanttila, Hong-Yi Chen
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Publication number: 20140201445Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness
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Publication number: 20140201326Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Patent number: 8769204Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.Type: GrantFiled: June 4, 2013Date of Patent: July 1, 2014Assignee: Marvell International Ltd.Inventors: Joseph Delgross, Sujat Jamil, R. Frank O'Bleness, Tom Hameenanttila, David E. Miner
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Patent number: 8688919Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.Type: GrantFiled: October 22, 2012Date of Patent: April 1, 2014Assignee: Marvell International Ltd.Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
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Patent number: 8631206Abstract: Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of the cache lines corresponds to one of a plurality of ways of the set-associative cache; a translation lookaside buffer to provide one of a plurality of way selections based on the set index of the virtual address and a virtual tag of the virtual address, wherein each of the way selections corresponds to one of the ways of the set-associative cache; and a way multiplexer to select one of the cache lines provided by the data cache based on the one of the plurality of way selections.Type: GrantFiled: August 20, 2008Date of Patent: January 14, 2014Assignee: Marvell International Ltd.Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila
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Patent number: 8533401Abstract: Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.Type: GrantFiled: December 30, 2002Date of Patent: September 10, 2013Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen
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Patent number: 8458404Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.Type: GrantFiled: August 13, 2009Date of Patent: June 4, 2013Assignee: Marvell International Ltd.Inventors: Joseph Delgross, Sujat Jamil, R. Frank O'Bleness, Tom Hameenanttila, David E. Miner
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Patent number: 8296525Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.Type: GrantFiled: August 7, 2009Date of Patent: October 23, 2012Assignee: Marvell International Ltd.Inventors: Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
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Patent number: 8135916Abstract: A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.Type: GrantFiled: April 1, 2009Date of Patent: March 13, 2012Assignee: Marvell International Ltd.Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl
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Patent number: 7966477Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.Type: GrantFiled: May 18, 2010Date of Patent: June 21, 2011Assignee: Marvell International Ltd.Inventors: Sujat Jamil, Hang Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Patent number: 7765349Abstract: A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.Type: GrantFiled: September 22, 2008Date of Patent: July 27, 2010Assignee: Marvell International Ltd.Inventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen
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Patent number: 7757046Abstract: A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.Type: GrantFiled: September 30, 2002Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Patent number: 7725683Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.Type: GrantFiled: September 25, 2003Date of Patent: May 25, 2010Assignee: Marvell International Ltd.Inventors: Sujat Jamil, Hang Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Patent number: 7694080Abstract: A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating frequency of the cache is higher than the operating frequency of the processor.Type: GrantFiled: December 29, 2004Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Quinn W. Merrell, R. Frank O'Bleness, Sujat Jamil, Hang T. Nguyen
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Patent number: 7685379Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.Type: GrantFiled: May 6, 2005Date of Patent: March 23, 2010Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Patent number: 7640387Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.Type: GrantFiled: March 31, 2008Date of Patent: December 29, 2009Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Steven J. Tu, Gregory W. Tse, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen
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Patent number: 7634603Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.Type: GrantFiled: July 25, 2008Date of Patent: December 15, 2009Assignee: Marvell International Ltd.Inventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen
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Patent number: 7487299Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.Type: GrantFiled: May 6, 2005Date of Patent: February 3, 2009Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Patent number: 7464227Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.Type: GrantFiled: December 10, 2002Date of Patent: December 9, 2008Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen