Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: Techniques for pushing data to multiple processors in a clean state.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-back caches, may snarf the data (obtain the cache line) if the required cache line is in a valid state in the agent's cache.

Abstract: A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to determine the load for each of the cache memories. Signals corresponding to the cache loads are generated and analyzed. A target processor is selected for a push data operation from a bus agent to the cache memory using the load information. The push operations to the caches are optimized based on the cache traffic information.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.

Abstract: A technique to write data to a processor cache without using intermediate memory storage. More particularly, embodiments of the invention relate to various techniques for writing data from a bus agent to a processor cache without having to first write the data to memory and then having the processor read the data from the memory.

Abstract: Methods and Apparatus for cache-to-cache transfers upon snooping a cache interconnect to detect a memory read request associated with a cache memory block cached in a first cache and a second cache. Upon a cache hit to a first and a second cache, supplying the cached memory block from the first cache or the second cache to a third cache based on a predetermined arbitration hierarchy.

Abstract: Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the first cache holds the memory block in an “owned” state, and the second cache holds the same memory block in a “shared” state. Main memory does not yet reflect modifications made to the memory block. When the processor associated with the first cache attempts to write-back the modified memory block to main memory, the second cache asserts a signal to the first cache which cancels the write-back. In addition, the memory block in the second cache changes to an “owned” state. If additional caches also hold the memory block, an arbitration mechanism selects one cache to be the new owner. In this manner, communications with main memory and power consumption are reduced.

Abstract: Methods and apparatus to detect memory address conflicts are disclosed. When a new cache line is allocated, the cache places the location where the cache line will be placed in a “pending” state until the cache line is retrieved. If a subsequent memory request is looking for an address in the pending cache line, that request is held back (e.g., delayed or replayed), until the cache line fill is complete and the “pending” status is removed. In this manner, the “pending” state, typically used to reserve cache locations, is also used to detect address conflicts.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.