Abstract: A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.

Abstract: A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.

Abstract: A power semiconductor device includes: a semiconductor body that conducts a load current between first and second load terminals at opposite first and second sides; a drift region of a first conductivity type; trenches extending from the first side towards the second side and each including a trench electrode; mesas laterally confined by the trenches and each including first and second type mesas; and semiconductor structures each including a serial connection of a first region of the first conductivity type coupled to or formed by the drift region, a second region of a second conductivity type and a third region of the first conductivity type coupled to the first load terminal by at least one of a first ohmic resistor and a Zener diode. Each first type mesa is electrically connected to the first load terminal and devoid of the semiconductor structures which are arranged in the second type mesas.

Abstract: A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body; a second load terminal at a second side of the semiconductor body opposite the first side, the power semiconductor device configured to conduct a load current between the load terminals; a control terminal at the first side configured to receive a control signal for controlling the load current; within an active region at least partially surrounded by an edge termination region, first trenches laterally confining mesas for conducting the load current, having control trenches electrically connected to the control terminal, and arranged in accordance with a first average pitch; and in a region laterally overlapping the control terminal, second trenches arranged in accordance with a second average pitch different from the first average pitch and electrically connected to the control terminal.

Abstract: An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

Abstract: An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least: an IGBT-only region, at least 90% of which is configured to conduct, based on a first control signal, only the forward load current; an RC IGBT region, at least 90% of which is configured to conduct the reverse load current and, based on a second control signal, the forward load current; and a hybrid region, at least 90% of which is configured to conduct, based on both the first control signal and the second control signal, the forward load current.

Abstract: A power transistor is formed by a plurality of transistor cells electrically connected in parallel. Each transistor cell includes a gate structure including a gate electrode coupled to a control terminal and a gate dielectric stack, the gate dielectric stack including a ferroelectric insulator. A method of operating the power transistor includes: switching the power transistor in a normal operating mode by applying a switching control signal to the control terminal, the switching control signal having a maximum voltage and a minimum voltage; and setting the ferroelectric insulator into a defined polarization state by applying a first voltage pulse to the control terminal, the first voltage pulse exceeding the maximum voltage of the switching control signal.

Abstract: A semiconductor device includes a semiconductor body having a trench transistor cell array. The trench transistor cell array includes a first trench transistor cell unit and a second trench transistor cell unit. Transistor cells based on the first trench transistor cell unit and transistor cells based on the second trench transistor cell unit are electrically connected in parallel. The first trench transistor cell unit has a first threshold voltage. The second trench transistor cell unit has a second threshold voltage larger than the first threshold voltage. An absolute value of dU/dt at turning on a nominal current of the transistor cell array is at least 50% of an absolute value of dU/dt at turning on 10% of the nominal current of the transistor cell array, dU/dt being the temporal derivate of a voltage U between load terminals of the trench transistor cell array.

Abstract: A power semiconductor device includes a first region in an active region of a semiconductor body and including first trenches each having a first trench electrode electrically connected to a gate terminal and a first trench insulator. A second region includes second trenches each having a second trench electrode electrically connected to the gate terminal and a second trench insulator. At least one of the following applies: a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; an average thickness of the second trench insulators amounts to at least 120% of an average thickness of the first trench insulators; a trench bottom thickness of each second trench insulator amounts to at least 120% of a corresponding trench bottom thickness of each first trench insulator; a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.

Abstract: A power semiconductor device includes: a semiconductor body coupled to first and second load terminals; an active region with first and second sections, both configured to conduct a load current between the load terminals; electrically isolated from the load terminals, first control electrodes in the first section and second control electrodes in both the first and second sections); and semiconductor channel structures in the semiconductor body extending in both the first and second sections. Each channel structure is associated to at least one of the first and second control electrodes. The respective control electrode is configured to induce an inversion channel for load current conduction in the associated semiconductor channel structure. The first section exhibits a first effective total inversion channel width per unit area ratio, W/A1, and the second section exhibits a second effective inversion channel width per unit area ratio, W/A2, where W/A1>W/A2.

Abstract: A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract: A bipolar semiconductor device and method are provided. One embodiment provides a bipolar semiconductor device including a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, and a plurality of third semiconductor regions of the first conductivity type at least partially arranged in the first semiconductor region and having a doping concentration which is higher than the first doping concentration. Each of the third semiconductor regions is provided with at least one respective junction termination structure.

Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.

Abstract: A first part of a semiconductor body is provided. Impurities are introduced into the first part of the semiconductor body, The impurities act as recombination centers in the semiconductor body and form a recombination Zone, and the impurities include at least a heavy metal. A second part of the semiconductor body is epitaxially produced on the first part after introducing the impurities in the first part. During epitaxially producing the second part of the semiconductor body on the first part of the semiconductor body, impurities in the first part of the semiconductor body are diffused to the second part of the semiconductor body.

Abstract: A first part of a semiconductor body is provided. Impurities are introduced into the first part of the semiconductor body, The impurities act as recombination centers in the semiconductor body and form a recombination Zone, and the impurities include at least a heavy metal. A second part of the semiconductor body is epitaxially produced on the first part after introducing the impurities in the first part. During epitaxially producing the second part of the semiconductor body on the first part of the semiconductor body, impurities in the first part of the semiconductor body are diffused to the second part of the semiconductor body.

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.