Patents by Inventor Frank Pfirsch

Frank Pfirsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190074352
    Abstract: A first part of a semiconductor body is provided. Impurities are introduced into the first part of the semiconductor body, The impurities act as recombination centers in the semiconductor body and form a recombination Zone, and the impurities include at least a heavy metal. A second part of the semiconductor body is epitaxially produced on the first part after introducing the impurities in the first part. During epitaxially producing the second part of the semiconductor body on the first part of the semiconductor body, impurities in the first part of the semiconductor body are diffused to the second part of the semiconductor body.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 7, 2019
    Inventors: Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 9954065
    Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Ingo Muri, Iris Moder, Johannes Baumgartl
  • Patent number: 9741795
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Publication number: 20170133465
    Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.
    Type: Application
    Filed: November 9, 2015
    Publication date: May 11, 2017
    Inventors: Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Ingo Muri, Iris Moder, Johannes Baumgartl
  • Patent number: 9608092
    Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Patent number: 9571087
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 9553178
    Abstract: A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 9543405
    Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Holger Ruething, Hans-Joachim Schulze, Frank Hille, Frank Pfirsch
  • Patent number: 9536958
    Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Frank Pfirsch, Hans-Joerg Timme
  • Publication number: 20160226477
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 4, 2016
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 9373692
    Abstract: A method for forming a field effect power semiconductor device includes providing a semiconductor body comprising a main horizontal surface and a conductive region arranged next to the main horizontal surface, forming an insulating layer on the main horizontal surface, and etching a narrow trench through the insulating layer so that a portion of the conductive region is exposed, the narrow trench comprising, in a given vertical cross-section, a maximum horizontal extension. The method further includes forming a vertical poly-diode structure comprising a horizontally extending pn-junction. Forming the vertical poly-diode structure includes depositing a polycrystalline semiconductor layer comprising a minimum vertical thickness of at least half of the maximum horizontal extension and maskless back-etching of the polycrystalline semiconductor layer to form a polycrystalline region in the narrow trench.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 9373700
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 9373710
    Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Vera Van Treek, Frank Pfirsch, Roman Baburske, Franz-Josef Niedernostheide
  • Patent number: 9362349
    Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Frank Pfirsch, Hans-Joachim Schulze, Carsten Schaeffer, Volodymyr Komarnitskyy, Anton Mauder, Holger Schulze, Gerhard Miller
  • Patent number: 9337185
    Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Carsten Schaeffer
  • Publication number: 20160111508
    Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Applicant: Infineon Technologies AG
    Inventors: Christian Foerster, Georg Ehrentraut, Frank Pfirsch, Thomas Raker
  • Patent number: 9312334
    Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Ruething, Frank Pfirsch, Armin Willmeroth, Frank Hille, Hans-Joachim Schulze
  • Publication number: 20160099707
    Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Publication number: 20160035862
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Publication number: 20160005818
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl