Patents by Inventor Frank Pfirsch

Frank Pfirsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9337185
    Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Carsten Schaeffer
  • Publication number: 20160111508
    Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Applicant: Infineon Technologies AG
    Inventors: Christian Foerster, Georg Ehrentraut, Frank Pfirsch, Thomas Raker
  • Patent number: 9312334
    Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Ruething, Frank Pfirsch, Armin Willmeroth, Frank Hille, Hans-Joachim Schulze
  • Publication number: 20160099707
    Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Publication number: 20160035862
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Publication number: 20160005818
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Patent number: 9231565
    Abstract: A circuit includes a bipolar transistor circuit including a first node, a second node, and a plurality of bipolar transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of bipolar transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the bipolar transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Patent number: 9231581
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 9219121
    Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor component including a semiconductor body having a cell array region with trenches and an edge region with pn junction. A transition region with at least one trench is formed between the cell array region and the edge region.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Frank Pfirsch
  • Patent number: 9214521
    Abstract: A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first type, a drift region of the second conductivity type, and a first electrode. The first and second emitter regions are arranged between the drift region and first electrode and each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source and body regions. A parasitic region of the first conductivity type is disposed outside the cell region and includes at least one section with charge carrier lifetime reduction means.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Frank Pfirsch, Hans-Joachim Schulze, Carsten Schaeffer, Volodymyr Komarnitskyy, Anton Mauder
  • Patent number: 9209109
    Abstract: An IGBT includes a semiconductor portion with IGBT cells. Each IGBT cell includes a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, and a drift zone of the first conductivity type separated from the source zone by the body zone. An emitter electrode includes a main layer and an interface layer. The interface layer directly adjoins at least one of the body zone and a supplementary zone of the second conductivity type. A contact resistance between the semiconductor portion and the interface layer is higher than between the semiconductor portion and a material of the main layer. For example, the interface layer may reduce diode emitter efficiency and reverse recovery losses in IGBTs.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Thomas Gutt, Mathias Plappert, Frank Pfirsch
  • Publication number: 20150349097
    Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Publication number: 20150333161
    Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Inventors: Vera Van Treek, Frank Pfirsch, Roman Baburske, Franz-Josef Niedernostheide
  • Patent number: 9190511
    Abstract: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 17, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Anton Mauder, Armin Willmeroth, Hans-Joachim Schulze, Stefan Sedlmaier, Markus Zundel, Franz Hirler, Arunjai Mittal
  • Patent number: 9171841
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 9166027
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Patent number: 9159819
    Abstract: A semiconductor device includes a drift zone of a first conductivity type in a semiconductor body. Controllable cells are configured to form a conductive channel connected with the drift zone in a first state. First zones of the first conductivity type as well as second zones and a third zone of a complementary second conductivity type are between the drift zone and a rear side electrode, respectively. The first, second and third zones directly adjoin the rear side electrode. The third zone is larger and has a lower mean emitter efficiency than the second zones.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 13, 2015
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber
  • Publication number: 20150279985
    Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Alexander Philippou, Johannes Georg Laven, Christian Jaeger, Frank Wolter, Frank Pfirsch, Antonio Vellei
  • Patent number: 9136397
    Abstract: A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: September 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Publication number: 20150236143
    Abstract: A semiconductor device includes a drift zone of a first conductivity type in a semiconductor body. Controllable cells are configured to form a conductive channel connected with the drift zone in a first state. First zones of the first conductivity type as well as second zones and a third zone of a complementary second conductivity type are between the drift zone and a rear side electrode, respectively. The first, second and third zones directly adjoin the rear side electrode. The third zone is larger and has a lower mean emitter efficiency than the second zones.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Inventors: Frank Pfirsch, Dorothea Werber