Abstract: An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated circuit is capable of performing one or more functions associated with the display of the content on the display panel. The apparatus further includes a controller capable of adjusting one or more characteristics of the display panel based on the amount of ambient light measured by the light sensor. The integrated circuit and the photo-sensitive device may be formed on one side of a semiconductor wafer, and the photo-sensitive device may be exposed to the ambient light through an opening in an opposing side of the semiconductor wafer.

Abstract: A method of forming a semiconductor device, the method including forming a substrate including a first surface having a non-doped region, forming an insulative material over the first surface of the substrate, forming a first conductive material over the first insulative material, forming an opening in the first conductive material that forms a path to the substrate that is substantially free of the first conductive material and the first insulative material, forming a second insulative material over the first conductive material, and forming a second conductive material over the second insulative material, wherein the second conductive material is formed in the opening and contacts the non-doped region of the substrate.

Abstract: A fluid ejection device including: a substrate having a first surface having an non-doped region; a first insulative material disposed on a portion of the first surface, the first insulative material having a plurality of openings forming a path to the first surface; a first conductive material disposed on the first insulative material, the first conductive material being disposed so that the plurality of openings are substantially free of the first conductive material; a second insulative material disposed on the first conductive material and portions of the first insulative material, the second insulative material being disposed so that the plurality of openings are substantial free of the second insulative material and a second conductive material being disposed on second insulative material and within plurality of openings so that some of the second conductive material disposed upon the second insulative material is in electrical contact with the non-doped region on the substrate.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.

Abstract: An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a pair of active areas formed in the first surface, a deposited oxide layer proximate the active areas, and a gate over the first surface between the pair of active areas.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.

Abstract: An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.

Abstract: A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A thin-film print head is provided that includes at least one MOSTFT transistor, at least one resistor, a conductive line between the transistor and resistor. External interconnects between the internal circuitry of print head and external driver circuitry are provided. The thin-film print head device is adjacent to an ink barrier and an orifice plate that together define the firing chamber. Each firing chamber has associated with it a respective thin-film resistor of the print head that is selectively driven by a respective transistor. The transistor includes a source, a gate, a channel, and a drain, wherein the source, channel, and drain are formed by a first polysilicon layer. The MOSTFT transistor selectively drives the resistor with sufficient current to vaporize ink in the chamber and eject ink therefrom.

Abstract: A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules.

Abstract: A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to form a passivation (24) to protect a circuit (16), is disclosed.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.