Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

Abstract: Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

Abstract: Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

Abstract: According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.

Abstract: Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. In one method, a first structure and a second structure is formed. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.

Abstract: Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

Abstract: Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.

Abstract: Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom.

Abstract: A method of forming sidewall spacers for a gate in a semiconductor device includes depositing a gate oxide layer over a gate and source/drain regions, and using a thermal anneal to oxidize silicon of the substrate and silicon of the gate after formation of the deposited oxide layer. A sidewall layer is deposited over the oxide layer following the oxidation, and the sidewall layer and oxide layer are patterned to form the sidewall spacers.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.

Abstract: Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.