Abstract: Methods are provided for fabricating a semiconductor device. A method forms a conductive fin arrangement on a first region of a semiconductor substrate. The method continues by forming a semiconductive resistor structure on a second region of the semiconductor substrate after forming the conductive fin arrangement, and forming a gate stack foundation structure overlying the conductive fin arrangement after forming the semiconductive resistor structure. The method removes portions of the gate stack foundation structure overlying the first region of the semiconductor substrate to define a gate structure for the semiconductor device.

Abstract: FIG. (1) and FIG. (2) show a top and bottom perspective of the device. Insulated Hook (12) is insulated and will be made of but not limited to, plastic, with a female screw receiving end adaptable to a standard piece of all-thread or install screw (14). Install screw ( )14 is a standard piece of all-thread cut to a desired length and will have hook (12) screwed on one end. The other end of install screw (14) will screw into hanger nut (16). Hanger nut (16) will be attached securely, for example by welding, to the bottom of body (18). The body (18) will envelope the adjust nut (20) and the adjust screw (22). Adjust screw (22) will be threaded into adjust nut (20) into and through the body (18). Body (18) will also house the toggle joint or pivot axle (24). Nose (28) will be attached to the body (18) by pivot axle (24). Wrapped around pivot axle (24) and anchored to the body (18) are the return springs (26a) and (26b). The return springs (26a) and (26b) will be pre-tensioned and attached also to the nose (28).

Abstract: Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

Abstract: Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: Some embodiments of a tobacco article may include tobacco disposed in a porous matrix. The tobacco article may provide tobacco, tobacco constituents, or both tobacco and tobacco constituents to the consumer's mouth in the form of particles, liquid, or vapor so as to provide tobacco satisfaction to the consumer. In some circumstances, the tobacco may be integrally molded with a plastic material so that at least a portion of the tobacco is disposed in pores of the matrix.

Abstract: Some embodiments of a tobacco article may include tobacco disposed in a porous matrix. The tobacco article may provide tobacco, tobacco constituents, or both tobacco and tobacco constituents to the consumer's mouth in the form of particles, liquid, or vapor so as to provide tobacco satisfaction to the consumer. In some circumstances, the tobacco may be integrally molded with a plastic material so that at least a portion of the tobacco is disposed in pores of the matrix.

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a conductive fin arrangement on a first region of a semiconductor substrate. The method further comprises forming a semiconductive resistor structure on a second region of the semiconductor substrate after forming the conductive fin arrangement, and forming a gate stack foundation structure overlying the conductive fin arrangement after forming the semiconductive resistor structure. The method further comprises removing portions of the gate stack foundation structure overlying the first region of the semiconductor substrate to define a gate structure for the semiconductor device.

Abstract: Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HPDCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

Abstract: A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

Abstract: A lockout device is provided for an instrument having a body and an actuating member extending from the body for operating the instrument. The lockout device includes a bottom member, a cover member, and a flexible member. The bottom member and cover member are adapted to receive a cinching portion of the flexible member between first and second holding surfaces of the bottom member and cover member. When the flexible member is wrapped around a portion of the body and received between the first and second holding surfaces and the cover member is in a closed position, the first and second holding surfaces prevent movement of a cinching portion of the flexible member.

Abstract: Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.

Abstract: Some embodiments of a tobacco article may include tobacco disposed in a porous matrix. The tobacco article may provide tobacco, tobacco constituents, or both tobacco and tobacco constituents to the consumer's mouth in the form of particles, liquid, or vapor so as to provide tobacco satisfaction to the consumer. In some circumstances, the tobacco may be integrally molded with a plastic material so that at least a portion of the tobacco is disposed in pores of the matrix.

Abstract: Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

Abstract: Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom.

Abstract: A lockout device is provided for an instrument having a body and an actuating member extending from the body for operating the instrument. The lockout device includes a bottom member, a cover member, and a flexible member. The bottom member and cover member are adapted to receive a cinching portion of the flexible member between first and second cinching features. One of the first and second cinching features includes at least one pin, and the other of the first and second cinching features includes at least one corresponding recess configured to receive the at least one pin. When the flexible member is wrapped around a portion of the body and received between the first and second cinching features and the cover member is in a closed position, the first and second cinching features prevent movement of a cinching portion of the flexible member.

Abstract: According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.

Abstract: Some embodiments of a tobacco product package device can be used to enhance freshness and other characteristics of tobacco products or other products contained therein. Certain features can improve product freshness both during shelf life and during consumer use.