Abstract: Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: Methods and apparatus relating to powering on devices via an intermediate computing device are described. In an embodiment, a request for data by a first device may be detected at a second device. The second device may determine a third device that stores the requested data and cause it to be turned on if the third device is in a reduced power consumption state. Other embodiments are also disclosed.

Abstract: In an embodiment, circuitry residing, at least in part, at a first network node may initiate, at least in part, replicating, at least in part, at the first node of a file space at a second network node, may detect, at least in part, modification at the second node of the file space, and may initiate, at least in part, corresponding modification at the first node of a replication of the file space. The circuitry also may generate, at least in part, an aggregated directory structure including, at least in part, the file space and another file space resident, at least in part, remotely from the second node. The directory structure may be provided, at least in part, to the second node prior, at least in part, to completion of the replicating, at least in part, at the first node of the file space.

Abstract: Systems and methods are provided through which automatic and adaptive use of active network performance measurement techniques identifies a fastest download source. Before a download source is selected, empirical measurements of the download speed are performed. For small files, the first source to acknowledge an open socket connection is used as an indication of the fastest download source. For large files, a download test is performed as the empirical measurement to determine the fastest download source.

Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

Abstract: In an embodiment, circuitry residing, at least in part, at a first network node may initiate, at least in part, replicating, at least in part, at the first node of a file space at a second network node, may detect, at least in part, modification at the second node of the file space, and may initiate, at least in part, corresponding modification at the first node of a replication of the file space. The circuitry also may generate, at least in part, an aggregated directory structure including, at least in part, the file space and another file space resident, at least in part, remotely from the second node. The directory structure may be provided, at least in part, to the second node prior, at least in part, to completion of the replicating, at least in part, at the first node of the file space.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: Methods and apparatus relating to powering on devices via an intermediate computing device are described. In an embodiment, a request for data by a first device may be detected at a second device. The second device may determine a third device that stores the requested data and cause it to be turned on if the third device is in a reduced power consumption state. Other embodiments are also disclosed.

Abstract: A host processor and a network processor may interact effectively, particularly with edge applications that involve tasks that are best handled independently by both the host and network processors. Data may be exchanged between the processors, for example, by simply passing pointers, avoiding the need for excessive data coping.

Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.