Patents by Inventor Frank Worrell

Frank Worrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9928193
    Abstract: A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: March 27, 2018
    Assignee: Cavium, Inc.
    Inventors: Frank Worrell, Bryan W. Chin
  • Patent number: 9667446
    Abstract: A condition code approach for comparing dimension match data of a rule with corresponding data in a key is provided. The approach includes, given dimension match data divided into first and second portions, comparing the first portion with a corresponding first portion of data in a key and setting a first condition code based on the comparison. The approach further includes comparing the second portion with a corresponding second portion of key data and setting a second condition code based on the comparison. The approach further includes determining whether the dimension match data is equal to, greater than, or less than the corresponding data in the key based on the first and second condition codes, and returning a response indicating whether the data matches based on the determination.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: May 30, 2017
    Assignee: CAVIUM, INC.
    Inventor: Frank Worrell
  • Patent number: 9568944
    Abstract: Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 14, 2017
    Assignee: CAVIUM, INC.
    Inventors: Frank Worrell, Bryan W. Chin
  • Patent number: 9544402
    Abstract: A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving value/mask values in a mask field, and for a given rule of rule chunk, encoding a priority field at the end of dimension data stored for the rule in the multi-rule. Advantageously, this approach provides efficient storage of rules and enables the efficient comparison of rules to keys.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 10, 2017
    Assignee: CAVIUM, INC.
    Inventors: Frank Worrell, Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Publication number: 20160139625
    Abstract: Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Inventors: Frank Worrell, Bryan W. Chin
  • Publication number: 20160140066
    Abstract: A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Inventors: Frank Worrell, Bryan W. Chin
  • Publication number: 20150193689
    Abstract: A condition code approach for comparing dimension match data of a rule with corresponding data in a key is provided. The approach includes, given dimension match data divided into first and second portions, comparing the first portion with a corresponding first portion of data in a key and setting a first condition code based on the comparison. The approach further includes comparing the second portion with a corresponding second portion of key data and setting a second condition code based on the comparison. The approach further includes determining whether the dimension match data is equal to, greater than, or less than the corresponding data in the key based on the first and second condition codes, and returning a response indicating whether the data matches based on the determination.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 9, 2015
    Inventor: Frank Worrell
  • Publication number: 20150189046
    Abstract: A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving value/mask values in a mask field, and for a given rule of rule chunk, encoding a priority field at the end of dimension data stored for the rule in the multi-rule. Advantageously, this approach provides efficient storage of rules and enables the efficient comparison of rules to keys.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Inventors: Frank Worrell, Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Patent number: 8046505
    Abstract: A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: October 25, 2011
    Assignee: LSI Corporation
    Inventors: Frank Worrell, Keith D. Au
  • Patent number: 7966431
    Abstract: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: June 21, 2011
    Assignee: LSI Corporation
    Inventors: Frank Worrell, Keith D. Au
  • Publication number: 20100325319
    Abstract: A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Inventors: Frank Worrell, Keith D. Au
  • Publication number: 20100321972
    Abstract: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Inventors: Frank Worrell, Keith D. Au
  • Patent number: 7797467
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: September 14, 2010
    Assignee: LSI Corporation
    Inventors: Frank Worrell, Keith D. Au
  • Patent number: 7681017
    Abstract: A pseudo pipeline including a plurality of pseudo pipeline stages and a control circuit. The control circuit may be configured to control the plurality of pseudo pipeline stages to provide pseudo pipelined operation.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: March 16, 2010
    Assignee: LSI Corporation
    Inventor: Frank Worrell
  • Publication number: 20070136503
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.
    Type: Application
    Filed: September 13, 2006
    Publication date: June 14, 2007
    Inventors: Frank Worrell, Keith Au
  • Publication number: 20070101089
    Abstract: A pseudo pipeline including a plurality of pseudo pipeline stages and a control circuit. The control circuit may be configured to control the plurality of pseudo pipeline stages to provide pseudo pipelined operation.
    Type: Application
    Filed: July 17, 2006
    Publication date: May 3, 2007
    Inventor: Frank Worrell
  • Publication number: 20070061554
    Abstract: A branch predictor, a method of predicting a conditional branch and a digital signal processor incorporating the conditional branch predictor or the method. In one embodiment, the branch predictor includes: (1) static branch correction logic configured to employ a static branch prediction and a correction indicator associated with a particular conditional branch in a computer program to generate a corrected branch prediction pertaining to the particular conditional branch and (2) confidence state updating logic associated with the static branch correction logic and configured to employ the static branch prediction and a branch taken indicator associated with the particular conditional branch to update a confidence state associated with the particular conditional branch, the correction indicator based on the confidence state.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 15, 2007
    Applicant: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 7069363
    Abstract: A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to a first clock edge and (ii) present a bus wait signal proximate a second clock edge. The slave interface may be configured to (i) present a command signal a delay after the first clock edge and (ii) receive a slave wait signal. The control logic may be configured to (i) register the early command signal to generate the command signal and (ii) convert the slave wait signal into the bus wait signal.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: June 27, 2006
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 6973561
    Abstract: A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: December 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Rene Vangemert, Frank Worrell, Gagan V. Gupta
  • Patent number: 6948054
    Abstract: A method of conditional branching in a pipelined processor. The method comprising the steps of (A) prefetching a branch target address in response to encountering a branch instruction, in prediction of taking a branch, and (B) evaluating between (i) taking the branch and (ii) not taking the branch substantially contemporaneously with prefetching the branch target address.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell