Abstract: An aging detector for an electrical circuit component and a method for monitoring an aging of a circuit component includes an input of the aging detector recording a parameter of the circuit component, with the aging circuit being configured to, based on the recorded parameter, determine a corresponding response threshold and/or a response or adapt the response threshold and/or the response, and to initiate the response to the parameter exceeding the specific response threshold.

Abstract: An aging detector for an electrical circuit component and a method for monitoring an aging of a circuit component includes an input of the aging detector recording a parameter of the circuit component, with the aging circuit being configured to, based on the recorded parameter, determine a corresponding response threshold and/or a response or adapt the response threshold and/or the response, and to initiate the response to the parameter exceeding the specific response threshold.

Abstract: An assembly of strip conductors for determining errors in a semiconductor circuit, the strip conductors may be situated on a level of the semiconductor circuit. The assembly includes multiple sections, the sections being arranged as a series circuit, each section including a number of strip conductors, the number of strip conductors in the particular sections being different, each section including a start area and an end area, a voltage difference value between the start area and the end area of the particular section being detectable, and the voltage difference values of the particular sections being different in the case of an error.

Abstract: A detector for determining a faulty semiconductor component including a semiconductor component, a contact-via chain, which is situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions, a guard ring, which is situated laterally at a distance from the semiconductor component, and an evaluation unit, which is situated on the semiconductor component, wherein the evaluation unit is designed to apply an electrical voltage to the contact-via chain, in particular a permanent electrical voltage, to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value.

Abstract: An apparatus for detecting a number of electrostatic discharges, comprises a discharge protection device, wherein a detection unit is disposed electrically in parallel with the discharge protection device, and the detection unit encompasses at least one memory block, the memory block having a reset input.

Abstract: An assembly of strip conductors for determining errors in a semiconductor circuit, the strip conductors may be situated on a level of the semiconductor circuit. The assembly includes multiple sections, the sections being arranged as a series circuit, each section including a number of strip conductors, the number of strip conductors in the particular sections being different, each section including a start area and an end area, a voltage difference value between the start area and the end area of the particular section being detectable, and the voltage difference values of the particular sections being different in the case of an error.

Abstract: A detector for determining a faulty semiconductor component including a semiconductor component, a contact-via chain, which is situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions, a guard ring, which is situated laterally at a distance from the semiconductor component, and an evaluation unit, which is situated on the semiconductor component, wherein the evaluation unit is designed to apply an electrical voltage to the contact-via chain, in particular a permanent electrical voltage, to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value.

Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Abstract: An integrated circuit part containing at least one MOS transistor with a trace system, with a source region having a source contact, and with a drain region having a drain contact, and with a gate region having a gate contact, and with a first cover layer lying on the gate, source, and drain regions and a first trace level formed thereupon, and with a second cover layer, lying above the first trace level, with a second trace level lying thereupon, and with a trace formed and connected with the source contact, and with a trace formed and connected with the drain contact, whereby a first metal region, arranged at least partially between the trace, connected to the source contact, and the trace, connected to the drain contact, is provided above the gate region lying on the first cover layer and/or the second cover layer, and the metal region is connected neither to the drain contact nor to the source contact or to the gate contact.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

Abstract: Semiconductor array and method for manufacturing a semiconductor array, wherein a conductive substrate (100), an element region (400), and an insulation layer (200), isolating the element region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the element region (400) as far as the insulation layer (200), the trench (700) is etched further in the insulation layer (200) as far as the conductive substrate (100), and within the trench (700), the conductive substrate (100) is at least partially etched to form conductive substrate regions (141, 142, 143, 144, 145, 146), isolated from one another.

Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

Abstract: A method for producing integrated microelectromechanical components is provided, whereby a first conductive layer is produced on a first insulating layer, the first conductive layer is structured, a second insulating layer is produced, a second conductive layer is produced, at least one etch opening is produced for at least partial etching of the second insulating layer beneath the second conductive layer in order to produce at least one hollow space, and at least a part of the first conductive layer and the second conductive layer is electrically contacted.

Abstract: A semiconductor arrangement for an integrated circuit is provided that includes a first region in which a number of components are formed, a second region, a buried insulating layer for vertically insulating the first region, an insulating structure, which is formed between the first region and the second region for laterally insulating the first region from the second region. The insulating structure can have a trench structure with a dielectric and a conductor structure with a semiconductor material. Whereby the trench structure borders on the buried insulating layer, and the conductor structure is designed to conductively connect the first region to the second region.

Abstract: A method for producing a nonvolatile memory cell in a semiconductor chip is provided, wherein a gate electrode is produced, a read region is produced, which together with the gate electrode forms a transistor arrangement, a first programming region is produced, which together with the gate electrode forms a first capacitor, a second programming region is produced, which together with the gate electrode forms a second capacitor, and a dielectric insulator is produced, which insulates the gate electrode from the read region and from the first programming region and from the second programming region. The gate electrode is deposited as a conductive layer on the dielectric insulator over the read region and also over the first programming region, as well as over the second programming region.

Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.