Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Abstract: At least one or more terminals of an integrated circuit, such as a low- or high-side driver stage, are protected against transient or over-voltages by two pairs of diodes. A first pair of diodes includes a regular diode (D1 or D1?) and a Zener-diode (ZD1 or ZD1?). A second pair of diodes also includes a regular diode (D2 or D3) and a Zener-diode (ZD2 or ZD3). These diode pairs are looped into the respective circuit and cooperate with an n-channel MOSFET or a p-channel MOSFET to provide the required over-voltage protection, particularly for transmitter/receiver circuits and databus systems especially in motor vehicles.

Abstract: A monolithically integratable semiconductor structure serves for over-voltage protection in an integrated circuit or as a normal diode. The structure includes an insulating layer between a substrate and a semiconductor layer of first conductivity type, and several layers formed in the semiconductor layer. First and second layers of second conductivity type are spaced apart from one another. A third layer of first conductivity type contacts the second layer. A fourth layer of first conductivity type directly contacts and surrounds the second and third layers. A fifth layer of first conductivity type and higher dopant concentration than the semiconductor layer is disposed under the first layer. The first layer surrounds the second, third and fourth layers essentially in a ring-shape. A first electrode contacts the first layer. A second electrode contacts the second and third layers.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relative to each other. In the method, a mask layer with a window therein is provided on a surface of a semiconductor body, and then a first doping step, a trench etching step, and a second doping step are carried out successively through this window while this one mask layer remains in place on the surface of the semiconductor body. Further etching and doping steps can be carried out successively also through this window of the mask layer.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: A monolithically integratable semiconductor structure serves for over-voltage protection in an integrated circuit or as a normal diode. The structure includes an insulating layer between a substrate and a semiconductor layer of first conductivity type, and several layers formed in the semiconductor layer. First and second layers of second conductivity type are spaced apart from one another. A third layer of first conductivity type contacts the second layer. A fourth layer of first conductivity type directly contacts and surrounds the second and third layers. A fifth layer of first conductivity type and higher dopant concentration than the semiconductor layer is disposed under the first layer. The first layer surrounds the second, third and fourth layers essentially in a ring-shape. A first electrode contacts the first layer. A second electrode contacts the second and third layers.

Abstract: At least one or more terminals of an integrated circuit, such as a low- or high-side driver stage, are protected against transient or over-voltages by two pairs of diodes. A first pair of diodes includes a regular diode (D1 or D1?) and a Zener-diode (ZD1 or ZD1?). A second pair of diodes also includes a regular diode (D2 or D3) and a Zener-diode (ZD2 or ZD3). These diode pairs are looped into the respective circuit and cooperate with an n-channel MOSFET or a p-channel MOSFET to provide the required over-voltage protection, particularly for transmitter/receiver circuits and databus systems especially in motor vehicles.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the bottom region.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.