Abstract: A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

Abstract: A method of forming a semiconductor includes forming a superjunction structure comprising a plurality of superjunction columns that alternate in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active area of the semiconductor substrate, each of the transistor cells being configured to control a vertical current flowing through superjunction structure, wherein forming the transistor cells includes forming source regions and body regions below the source regions; wherein forming the body regions includes forming a body layer extending from a main surface of the semiconductor substrate, wherein a dopant profile of second conductivity type dopants in the body layer increases moving from the main surface into the semiconductor substrate until it reaches a maximum at first depth from the main surface, and wherein the first depth is below a bottom depth of the source regions.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: Disclosed is a transistor device. In an embodiment, the transistor device includes a plurality of transistor cells and a source electrode. Each of the transistor cells includes: a source region of a first doping type; a body region of a second doping type complementary to the first doping type and adjoining the source region; a gate electrode adjacent to the body region, dielectrically insulated from the body region by a gate dielectric, and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body; and a body contact region adjoining the body region and electrically connected to the source electrode. A distance between the body contact region and the gate dielectric is less than 300 nanometers.

Abstract: Disclosed is method for producing a transistor device and a transistor device. The transistor device includes a gate arrangement. The gate arrangement includes: a plurality of gate electrodes, each gate electrode being arranged in a respective gate trench extending from a first surface of a semiconductor body into the semiconductor body and dielectrically insulated from the semiconductor body by a respective gate dielectric; an insulating layer above the first surface of the semiconductor body and the gate electrodes; at least one contact opening in the insulating layer above each gate electrode; a plurality of contact fingers, each contact finger being connected to a respective gate electrode in a respective contact opening; and a connector connecting the contact fingers with each other.

Abstract: Disclosed is a transistor device with an edge termination structure and a method. The method includes forming an edge termination structure of a transistor device. Forming the edge termination structure includes: forming an edge trench in an edge region of a semiconductor body such that the edge trench has a trench bottom and an inner trench sidewall facing an inner region of the semiconductor body; and forming a first edge region of a second doping type adjacent to the inner trench sidewall. Forming the first edge region includes implanting dopant atoms of the second doping type at least into the inner trench sidewall.

Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Abstract: A semiconductor arrangement and an electronic circuit with a semiconductor arrangement are disclosed. The semiconductor arrangement includes: a semiconductor body having a first region of a first doping type, a second region of the first doping type, and a third region of a second doping type complementary to the first doping type; and a guard structure arranged in the third region between the first and second regions. The first and second regions are spaced apart from each other in a lateral direction of the semiconductor body, and the third region is arranged between the first and second regions. The guard structure includes a first guard region and a second guard region arranged next to each other in the first lateral direction. The first guard region includes a doped region of the second doping type. The second guard region includes a doped region of the first doping type.

Abstract: A semiconductor device includes a semiconductor body, a vertical transistor arranged in a first device region of the semiconductor body, and a lateral transistor arranged in a second device region of the semiconductor body. The vertical transistor includes a plurality of drift regions of a first doping type and a plurality of compensation regions of a second doping type complementary to the first doping type. The drift regions and the compensation regions are arranged alternately in a lateral direction of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The lateral transistor includes device regions arranged in the first semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type which has a first surface. A first device region formed in the semiconductor substrate has the first conductivity type and a lateral extent that is less than the lateral extent of the first surface of the semiconductor substrate. The first device region is electrically separated from the semiconductor substrate by an isolation structure. The isolation structure includes a buried layer which is doped with a second conductivity type that opposes the first conductivity type and further includes a first elongate sinker of the second conductivity type. The first elongate sinker extends from the first surface into the semiconductor substrate and is in electrical contact with the buried layer. The semiconductor device further includes a breakdown voltage influencing structure of the second conductivity type that is arranged in the semiconductor substrate and laterally adjacent the buried layer.

Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Abstract: A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

Abstract: A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Abstract: A transistor device is disclosed.