Patents by Inventor Franz Hirler

Franz Hirler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10679855
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10651271
    Abstract: A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Christian Fachmann, Franz Hirler, Maximilian Treiber
  • Publication number: 20200127102
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 23, 2020
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10629690
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift zone of a first conductivity type adjacent to a drain region, and a first field plate and a second field plate adjacent to the drift zone. The second field plate is arranged between the first field plate and the drain region. The second field plate is electrically connected to a contact portion arranged in the drift zone. The transistor further includes an intermediate portion of the first conductivity type at a lower doping concentration than the drift zone. A distance between the intermediate portion and the drain region is smaller than the distance between the contact portion and the drain region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Franz Hirler, Till Schloesser
  • Publication number: 20200105918
    Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 2, 2020
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
  • Publication number: 20200091300
    Abstract: A transistor device includes, in a semiconductor body, a drift region, a body region, and a source region separated from the drift region by the body region and connected to a source node. The transistor device further includes a gate electrode dielectrically insulated from the body region by a gate dielectric, and a field electrode structure. The field electrode structure includes: a first field electrode connected to the source node and dielectrically insulated from the drift region by a first field electrode dielectric; a second field electrode dielectrically insulated from the drift region by a second field electrode dielectric; and a coupling circuit connected between the second field electrode and the source node and configured to connect the second field electrode to the source node dependent on a voltage between the source node and the second field electrode.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 19, 2020
    Inventors: Franz Hirler, Cesar Augusto Braz, Gerhard Noebauer, Martin Henning Vielemeyer
  • Patent number: 10580873
    Abstract: In an embodiment, a power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions and a drift volume in the semiconductor body; a semiconductor zone in the semiconductor body and coupling the drift volume to the second load terminal, a first transition established between the semiconductor zone and the drift volume; a control electrode insulated from the semiconductor body and the load terminals and configured to control a path of the load current in the channel region; and a trench extending into the drift volume along an extension direction and including a field electrode. A cross-sectional area of the field electrode is smaller than a cross-sectional area of the control electrode in a plane parallel to the extension direction.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Publication number: 20200044019
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Patent number: 10553681
    Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Franz Hirler, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10547291
    Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Publication number: 20200027949
    Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
  • Patent number: 10541327
    Abstract: A semiconductor device includes a trench structure extending into a semiconductor body from a first surface. The trench structure has a shield electrode, a dielectric structure and a diode structure. The diode structure is arranged at least partly between the first surface and a first part of the dielectric structure. The shield electrode is arranged between the first part of the dielectric structure and a bottom of the trench structure. The shield electrode and the semiconductor body are electrically isolated by the dielectric structure. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler
  • Patent number: 10510846
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10504891
    Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 10, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler, Maximilian Treiber
  • Patent number: 10490656
    Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Uwe Wahl
  • Patent number: 10468479
    Abstract: A semiconductor device includes a semiconductor body, which includes transistor cells and a drift zone between a drain layer and the transistor cells. The drift zone includes a compensation structure. Above a depletion voltage a first output charge gradient obtained by increasing a drain-to-source voltage from the depletion voltage to a maximum drain-to-source voltage deviates by less than 5% from a second output charge gradient obtained by decreasing the drain-to-source voltage from the maximum drain-to-source voltage to the depletion voltage. At the depletion voltage the first output charge gradient exhibits a maximum curvature.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
  • Publication number: 20190334000
    Abstract: A transistor component includes at least one transistor cell having: a drift region, a source region, a body region and a drain region in a semiconductor body, the body region being arranged between the source and drift regions, and the drift region being arranged between the body and drain regions; a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric; and a field electrode arranged adjacent to the drift region and dielectrically isolated from the drift region by a field electrode dielectric. The field electrode dielectric has a thickness that increases in a direction toward the drain region. The drift region has, in a mesa region adjacent to the field electrode, a doping concentration that increases in the direction toward the drain region.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Franz Hirler, Andrew Christopher Graeme Wood
  • Patent number: 10453931
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20190319124
    Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 17, 2019
    Inventors: Andreas Riegler, Christian Fachmann, Bjoern Fischer, Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: RE47710
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth