Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Abstract: A semiconductor device includes a trench structure extending into a semiconductor body from a first surface. The trench structure has a shield electrode, a dielectric structure and a diode structure. The diode structure is arranged at least partly between the first surface and a first part of the dielectric structure. The shield electrode is arranged between the first part of the dielectric structure and a bottom of the trench structure. The shield electrode and the semiconductor body are electrically isolated by the dielectric structure. Corresponding methods of manufacture are also described.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor.

Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.

Abstract: A semiconductor device includes a semiconductor body, which includes transistor cells and a drift zone between a drain layer and the transistor cells. The drift zone includes a compensation structure. Above a depletion voltage a first output charge gradient obtained by increasing a drain-to-source voltage from the depletion voltage to a maximum drain-to-source voltage deviates by less than 5% from a second output charge gradient obtained by decreasing the drain-to-source voltage from the maximum drain-to-source voltage to the depletion voltage. At the depletion voltage the first output charge gradient exhibits a maximum curvature.

Abstract: A transistor component includes at least one transistor cell having: a drift region, a source region, a body region and a drain region in a semiconductor body, the body region being arranged between the source and drift regions, and the drift region being arranged between the body and drain regions; a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric; and a field electrode arranged adjacent to the drift region and dielectrically isolated from the drift region by a field electrode dielectric. The field electrode dielectric has a thickness that increases in a direction toward the drain region. The drift region has, in a mesa region adjacent to the field electrode, a doping concentration that increases in the direction toward the drain region.

Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.

Abstract: A semiconductor device includes a transistor arrangement and a diode structure. The diode structure is coupled between a gate electrode structure of the transistor arrangement and a source electrode structure of the transistor arrangement. An insulating layer is located vertically between the diode structure and a front side surface of a semiconductor substrate of the semiconductor device. The diode structure includes at least one diode pn-junction. A substrate pn-junction extends from the front side surface of the semiconductor substrate into the semiconductor substrate between a shielding doping region and an edge doping portion. The edge doping portion is located adjacent to the shielding doping region within the semiconductor substrate. At the front side surface of the semiconductor substrate, the substrate pn-junction is located laterally between the diode pn-junction and a source contact region of the diode structure with the source electrode structure.

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.

Abstract: A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.

Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.

Abstract: In an embodiment, a power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions and a drift volume in the semiconductor body; a semiconductor zone in the semiconductor body and coupling the drift volume to the second load terminal, a first transition established between the semiconductor zone and the drift volume; a control electrode insulated from the semiconductor body and the load terminals and configured to control a path of the load current in the channel region; and a trench extending into the drift volume along an extension direction and including a field electrode. A cross-sectional area of the field electrode is smaller than a cross-sectional area of the control electrode in a plane parallel to the extension direction.

Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.