Patents by Inventor Franz Hofmann

Franz Hofmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190120435
    Abstract: The present invention relates to a pressure tank arrangement for storing and discharging compressed liquid fuels and to a method for producing a pressure tank arrangement of this type. Here, force transmission elements of the pressure tank arrangement are arranged in such a way that they utilize the available installation space for pressure tank arrangements of this type in an optimum manner.
    Type: Application
    Filed: July 11, 2016
    Publication date: April 25, 2019
    Inventors: Thomas LANZL, Franz HOFMANN, Andreas GRUHL
  • Patent number: 10186515
    Abstract: The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: January 22, 2019
    Assignee: SOITEC
    Inventor: Franz Hofmann
  • Patent number: 9956712
    Abstract: The invention relates to a method for producing a pressure accumulator (1), in particular for storing hydrogen in motor vehicles. First, a pressure accumulator liner (3) which has at least one pole cap (2, 2?) is produced preferably by means of a plastic blow molding method, and the outside of the liner (3) is then provided, preferably braided, with a multi-ply reinforcing layer (9), which has reinforcing fibers (8). According to the invention, a fiber supply cap (10, 10?) is applied on the pole cap (2, 2?) prior to applying the reinforcing fibers (8), the outer surface of the fiber supply cap being spaced from the pole region (21, 21?) of the pole cap (2, 2?).
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 1, 2018
    Assignee: REHAU AG+CO
    Inventors: Thomas Lanzl, Franz Hofmann, Markus Friederich, Marina Feist, Andreas Gruhl
  • Patent number: 9816668
    Abstract: The present invention relates to a device for the storage and delivery of liquid and/or gaseous media under pressure, having a media container (1) of a plastics material, preferably of polyamide, receiving the medium, at least one valve connection element (2), connected to the media container (1), and at least one valve element (3, 3a, 3b), connectable to the valve connection element (2), wherein the media container (1) has a collar (4), which is molded on in one piece and protrudes from the media container (1) and has a collar outer wall (5) and a collar inner wall (6).
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 14, 2017
    Assignee: REHAU AG + CO.
    Inventors: Thomas Lanzl, Franz Hofmann
  • Publication number: 20170165894
    Abstract: The invention relates to a method for producing a pressure accumulator (1), in particular for storing hydrogen in motor vehicles. First, a pressure accumulator liner (3) which has at least one pole cap (2, 2?) is produced preferably by means of a plastic blow molding method, and the outside of the liner (3) is then provided, preferably braided, with a multi-ply reinforcing layer (9), which has reinforcing fibers (8). According to the invention, a fiber supply cap (10, 10?) is applied on the pole cap (2, 2?) prior to applying the reinforcing fibers (8), the outer surface of the fiber supply cap being spaced from the pole region (21, 21?) of the pole cap (2, 2?).
    Type: Application
    Filed: November 5, 2014
    Publication date: June 15, 2017
    Inventors: Thomas LANZL, Franz HOFMANN, Markus FRIEDERICH, Marina FEIST, Andreas GRUHL
  • Patent number: 9640664
    Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 2, 2017
    Assignee: Soitec
    Inventor: Franz Hofmann
  • Patent number: 9472469
    Abstract: This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 18, 2016
    Assignee: Soitec
    Inventors: Gerhard Enders, Franz Hofmann
  • Publication number: 20160020326
    Abstract: The present invention relates to a double-gate finFET comprising: at least two fins (FIN) realizing a single channel; a back-gate (BG) placed between the fins; and a front-gate (FG), placed outside of the fins. Further, the invention relates to a manufacturing process, resulting in the double-gate finFET.
    Type: Application
    Filed: March 13, 2014
    Publication date: January 21, 2016
    Inventors: Carlos MAZURE, Franz HOFMANN
  • Publication number: 20150362130
    Abstract: The present invention relates to a device for the storage and delivery of liquid and/or gaseous media under pressure, having a media container (1) of a plastics material, preferably of polyamide, receiving the medium, at least one valve connection element (2), connected to the media container (1), and at least one valve element (3, 3a, 3b), connectable to the valve connection element (2), wherein the media container (1) has a collar (4), which is moulded on in one piece and protrudes from the media container (1) and has a collar outer wall (5) and a collar inner wall (6).
    Type: Application
    Filed: February 6, 2014
    Publication date: December 17, 2015
    Inventors: THOMAS LANZL, FRANZ HOFMANN
  • Publication number: 20150357333
    Abstract: This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.
    Type: Application
    Filed: December 12, 2013
    Publication date: December 10, 2015
    Inventors: Gerhard Enders, Franz Hofmann
  • Publication number: 20150214372
    Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.
    Type: Application
    Filed: September 10, 2013
    Publication date: July 30, 2015
    Applicant: SOITEC
    Inventor: Franz Hofmann
  • Publication number: 20150171094
    Abstract: The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.
    Type: Application
    Filed: July 4, 2013
    Publication date: June 18, 2015
    Applicant: Soitec
    Inventor: Franz Hofmann
  • Patent number: 8702921
    Abstract: A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 22, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alexander Frey, Franz Hofmann, Birgit Holzapfl, Christian Paulus, Meinrad Schienle, Roland Thewes
  • Patent number: 8492844
    Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 23, 2013
    Assignee: Soitec
    Inventors: Gerhard Enders, Wolfgang Hoenlein, Franz Hofmann, Carlos Mazure
  • Patent number: 8480877
    Abstract: A sensor arrangement for detecting particles potentially contained in an analyte is disclosed. The arrangement includes a substrate; at least one sensor electrode which is arranged on and/or in the substrate and on which scavenger molecules, which hybridize with particles that are potentially contained in an analyte and are to be detected, are immobilized, electrically charged particles generated by hybridization being detectable on the at least one sensor electrode; and at least one diffusion detection electrode which is arranged in a surrounding region of the at least one sensor electrode and is embodied in such a way that it detects electrically charged particles that are generated by hybridization and can be diffused away by the at least one sensor electrode.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: July 9, 2013
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alexander Frey, Franz Hofmann
  • Patent number: 8258564
    Abstract: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: September 4, 2012
    Assignee: Qimonda AG
    Inventors: Josef Willer, Franz Hofmann, Michael Specht, Christoph Friederich, Doris Keitel-Schulz, Lars Bach, Thomas Melde
  • Patent number: 8241989
    Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 14, 2012
    Assignee: Qimonda AG
    Inventor: Franz Hofmann
  • Patent number: 8097915
    Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: January 17, 2012
    Assignee: Qimonda AG
    Inventors: Wolfgang Rösner, Franz Hofmann, Michael Specht, Martin Städele, Johannes Luyken
  • Patent number: 8067249
    Abstract: A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: November 29, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alexander Frey, Franz Hofmann, Petra Schindler-Bauer
  • Patent number: 7915667
    Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Roman Knoefler, Michael Specht, Franz Hofmann, Florian Beug, Dirk Manger, Stephan Riedel