Patents by Inventor Franz Hofmann
Franz Hofmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8097915Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.Type: GrantFiled: May 31, 2005Date of Patent: January 17, 2012Assignee: Qimonda AGInventors: Wolfgang Rösner, Franz Hofmann, Michael Specht, Martin Städele, Johannes Luyken
-
Patent number: 8067249Abstract: A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.Type: GrantFiled: March 18, 2005Date of Patent: November 29, 2011Assignee: Siemens AktiengesellschaftInventors: Alexander Frey, Franz Hofmann, Petra Schindler-Bauer
-
Patent number: 7915667Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.Type: GrantFiled: June 11, 2008Date of Patent: March 29, 2011Assignee: Qimonda AGInventors: Roman Knoefler, Michael Specht, Franz Hofmann, Florian Beug, Dirk Manger, Stephan Riedel
-
Patent number: 7893519Abstract: An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.Type: GrantFiled: May 28, 2008Date of Patent: February 22, 2011Assignee: Qimonda AGInventor: Franz Hofmann
-
Patent number: 7838925Abstract: An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.Type: GrantFiled: July 15, 2008Date of Patent: November 23, 2010Assignee: Qimonda AGInventors: Wolfgang Roesner, Franz Hofmann
-
Patent number: 7829892Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.Type: GrantFiled: October 29, 2007Date of Patent: November 9, 2010Assignee: Qimonda AGInventors: Richard Johannes Luyken, Franz Hofmann, Lothar Risch, Dirk Manger, Wolfgang Roesner, Till Schloesser, Michael Specht
-
Patent number: 7778073Abstract: Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.Type: GrantFiled: October 15, 2007Date of Patent: August 17, 2010Assignee: Qimonda AGInventors: Josef Willer, Franz Hofmann, Detlev Richter, Nicolas Nagel
-
Patent number: 7772580Abstract: In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.Type: GrantFiled: August 10, 2007Date of Patent: August 10, 2010Assignee: Qimonda AGInventors: Franz Hofmann, Josef Willer
-
Patent number: 7767567Abstract: Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.Type: GrantFiled: September 29, 2006Date of Patent: August 3, 2010Assignee: Qimonda AGInventors: Josef Willer, Franz Hofmann
-
Publication number: 20100123202Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.Type: ApplicationFiled: November 14, 2008Publication date: May 20, 2010Applicant: QIMONDA AGInventor: Franz Hofmann
-
Patent number: 7719059Abstract: A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.Type: GrantFiled: October 27, 2006Date of Patent: May 18, 2010Assignee: Infineon Technologies AGInventors: Franz Hofmann, Erhard Landgraf, Richard Johannes Luyken
-
Patent number: 7714377Abstract: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.Type: GrantFiled: April 19, 2007Date of Patent: May 11, 2010Assignees: Qimonda AG, Qimonda Flash GmbHInventors: Michael Specht, Nicolas Nagel, Franz Hofmann, Thomas Mikolajick
-
Patent number: 7709827Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.Type: GrantFiled: October 29, 2003Date of Patent: May 4, 2010Assignee: Qimonda, AGInventors: Andrew Graham, Franz Hofmann, Wolfgang Hönlein, Johannes Kretz, Franz Kreupl, Erhard Landgraf, Johannes Richard Luyken, Wolfgang Rösner, Thomas Schulz, Michael Specht
-
Patent number: 7700427Abstract: Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.Type: GrantFiled: June 13, 2007Date of Patent: April 20, 2010Assignee: Qimonda AGInventors: Michael Specht, Franz Hofmann, Wolfgang Roesner, Guerkan Ilicali
-
Patent number: 7692246Abstract: The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b?; 113b?). Formation of the fin-like channel region (113b?; 113b?) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1?-S4?); anisotropic etching of the active region (1) using the modified hard mask (S1?-S4?) forming widened STI trenches (G1?-G5?), the fin-like channel regions (113b?; 113b?) of the active region (1) remaining for each individual FinFET transistor.Type: GrantFiled: January 4, 2007Date of Patent: April 6, 2010Assignee: Infineon Technologies AGInventors: Lars Dreeskornfeld, Franz Hofmann, Johannes Richard Luyken, Michael Specht
-
Publication number: 20100013005Abstract: An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Applicant: QIMONDA AGInventors: Wolfgang Roesner, Franz Hofmann
-
Patent number: 7635867Abstract: A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer.Type: GrantFiled: May 16, 2002Date of Patent: December 22, 2009Assignee: Infineon Technologies AGInventors: Andrew Graham, Franz Hofmann, Johannes Kretz, Franz Kreupl, Richard Luyken, Wolfgang Rösner
-
Publication number: 20090309152Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Inventors: Roman Knoefler, Michael Specht, Franz Hofmann, Florian Beug, Dirk Manger, Stephan Riedel
-
Publication number: 20090308741Abstract: A sensor arrangement for detecting particles potentially contained in an analyte is disclosed. The arrangement includes a substrate; at least one sensor electrode which is arranged on and/or in the substrate and on which scavenger molecules, which hybridize with particles that are potentially contained in an analyte and are to be detected, are immobilized, electrically charged particles generated by hybridization being detectable on the at least one sensor electrode; and at least one diffusion detection electrode which is arranged in a surrounding region of the at least one sensor electrode and is embodied in such a way that it detects electrically charged particles that are generated by hybridization and can be diffused away by the at least one sensor electrode.Type: ApplicationFiled: May 24, 2005Publication date: December 17, 2009Inventors: Alexander Frey, Franz Hofmann
-
Publication number: 20090294895Abstract: An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Applicant: QIMONDA AGInventor: Franz Hofmann