Patents by Inventor Franz P. Clarberg

Franz P. Clarberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10762700
    Abstract: Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling distributions over an arbitrary domain can be efficiently generated in up to five dimensions. Sample placement allows pseudo-random, stratified random, or blue noise sampling. Random sampling with an adaptive density function may be achieved by adding one dimension.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Franz P. Clarberg
  • Patent number: 10354432
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Franz P. Clarberg, Magnus Andersson, Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller
  • Patent number: 10164458
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 10164459
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 10134160
    Abstract: Visibility may be analytically resolved rather than using point-sampling, thereby entirely avoiding geometric aliasing and the need to store multiple samples per pixel. By relying on existing techniques for shading, i.e., by shading once per fragment and focusing on visibility, visual results may be equivalent to multi-sampled anti-aliasing (MSAA) using an infinite sampling rate in some embodiments.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventor: Franz P. Clarberg
  • Patent number: 10074213
    Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
  • Patent number: 9990748
    Abstract: The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Robert M. Toth, Larry Seiler
  • Patent number: 9965892
    Abstract: A moving or defocused geometry may be stochastically rendered by grouping a plurality of primitives of that geometry in a hierarchical data structure. Visible fragments may be located in that data structure by hierarchically traversing a ray frustum through the structure. A time-dependent ray tracing data structure may be used in some embodiments.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Christopher A. Burns
  • Patent number: 9959643
    Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
  • Patent number: 9906816
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
  • Patent number: 9892053
    Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
  • Publication number: 20170264106
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170256079
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: April 20, 2017
    Publication date: September 7, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170213384
    Abstract: Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling distributions over an arbitrary domain can be efficiently generated in up to five dimensions. Sample placement allows pseudo-random, stratified random, or blue noise sampling. Random sampling with an adaptive density function may be achieved by adding one dimension.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 27, 2017
    Inventor: Franz P. Clarberg
  • Publication number: 20170206700
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 20, 2017
    Inventors: CARL J. MUNKBERG, JON N. HASSELGREN, FRANZ P. CLARBERG, MAGNUS ANDERSSON, ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER
  • Patent number: 9672657
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Grant
    Filed: September 10, 2016
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Patent number: 9659393
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170142447
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Application
    Filed: October 19, 2016
    Publication date: May 18, 2017
    Inventors: ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER, FRANZ P. CLARBERG
  • Publication number: 20170124742
    Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
  • Patent number: 9569878
    Abstract: Thin invention introduces a five-dimensional rasterization technique that uses a test based on triangle edges in order to obtain high efficiency. A compact formulation of five-dimensional edge equations is used to derive a conservative triangle edge versus tile test in five dimensions, expressed as an affine hyperplane.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Franz P. Clarberg