Patents by Inventor Franz P. Clarberg
Franz P. Clarberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170011545Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.Type: ApplicationFiled: September 10, 2016Publication date: January 12, 2017Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
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Patent number: 9542776Abstract: Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling distributions over an arbitrary domain can be efficiently generated in up to five dimensions. Sample placement allows pseudo-random, stratified random, or blue noise sampling. Random sampling with an adaptive density function may be achieved by adding one dimension.Type: GrantFiled: June 13, 2012Date of Patent: January 10, 2017Assignee: Intel CorporationInventor: Franz P. Clarberg
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Patent number: 9491490Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.Type: GrantFiled: June 12, 2015Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Möller, Franz P. Clarberg
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Patent number: 9483869Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.Type: GrantFiled: May 12, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
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Publication number: 20160283391Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Inventors: Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
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Publication number: 20160275701Abstract: The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.Type: ApplicationFiled: March 18, 2015Publication date: September 22, 2016Inventors: Franz P. Clarberg, Robert M. Toth, Larry Seiler
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Patent number: 9406100Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.Type: GrantFiled: November 3, 2015Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
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Patent number: 9390541Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.Type: GrantFiled: April 9, 2013Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
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Publication number: 20160055614Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.Type: ApplicationFiled: November 3, 2015Publication date: February 25, 2016Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
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Patent number: 9183652Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.Type: GrantFiled: May 15, 2013Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
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Patent number: 9183608Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.Type: GrantFiled: December 23, 2009Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
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Patent number: 9142008Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.Type: GrantFiled: September 10, 2014Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Franz P. Clarberg, Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller
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Publication number: 20150206340Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.Type: ApplicationFiled: May 12, 2014Publication date: July 23, 2015Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
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Publication number: 20150154772Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.Type: ApplicationFiled: May 13, 2013Publication date: June 4, 2015Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
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Publication number: 20150145873Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.Type: ApplicationFiled: December 23, 2009Publication date: May 28, 2015Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
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Patent number: 9038034Abstract: During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the compilation, and the bounds together with other metadata are used to generate an optimized culling program. If not possible, then an assumption may be made and the assumption used to compile the code. If the assumption proves to be invalid, a new assumption could be made and the code may be recompiled in some embodiments.Type: GrantFiled: December 22, 2009Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg, Robert M. Toth
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Publication number: 20150097857Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
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Publication number: 20150084981Abstract: Visibility may be analytically resolved rather than using point-sampling, thereby entirely avoiding geometric aliasing and the need to store multiple samples per pixel. By relying on existing techniques for shading, i.e., by shading once per fragment and focusing on visibility, visual results may be equivalent to multi-sampled anti-aliasing (MSAA) using an infinite sampling rate in some embodiments.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventor: Franz P. Clarberg
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Publication number: 20150070355Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.Type: ApplicationFiled: March 27, 2014Publication date: March 12, 2015Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
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Publication number: 20150022532Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.Type: ApplicationFiled: September 10, 2014Publication date: January 22, 2015Inventors: Franz P. Clarberg, Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller