Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.

Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.

Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a bonded pair of wafers, where the bonded pair of wafers are bonded with a bonding tool. The wafer shape metrology sub-system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; convert the stress-free shape measurements into an overlay distortion pattern; detect one or more localized deviations in the bonded pair of wafers in order to identify one or more contaminant particles on the bonding tool; and report the one or more localized deviations in the bonded pair of wafers.

Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform stress-free shape measurements on an active wafer, a carrier wafer, and a bonded device wafer. The active wafer includes functioning logic circuitry and the carrier wafer is electrically passive. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements; determine overlay distortion between features on the active wafer and the carrier wafer; and convert the overlay distortion to a feed-forward correction for one or more lithographic scanners. The controller is also configured to determine a control range for a bonder or lithography scanner; predict an overlay distortion pattern; calculate an optimal control signature based on a minimal achievable overlay; and provide a feed-forward correction to the bonder or lithography scanner based on the calculated optimal control signature.

Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.

Abstract: A system for controlling an etch process includes an etching tool, a metrology tool, and a controller. The etching tool is controllable via a set of control parameters and may execute a plurality of etch recipes containing values of the set of control parameters. The controller may direct the etching tool to execute a plurality of etch recipes on a plurality of metrology targets; direct the metrology tool to generate metrology data indicative of two or more etch characteristics on the plurality of metrology targets; determine one or more relationships between the two or more etch characteristics and the set of control parameters based on the metrology data; and generate, based on the one or more relationships, a particular etch recipe to constrain one of the two or more etch characteristics and maintain the remainder of the two or more etch characteristics within defined bounds.

Abstract: A system for controlling an etch process includes and etching tool, a metrology tool, and a controller. The etching tool is controllable via a set of control parameters and may execute a plurality of etch recipes containing values of the set of control parameters. The controller may direct the etching tool to execute a plurality of etch recipes on a plurality of metrology targets; direct the metrology tool to generate metrology data indicative of two or more etch characteristics on the plurality of metrology targets; determine one or more relationships between the two or more etch characteristics and the set of control parameters based on the metrology data; and generate, based on the one or more relationships, a particular etch recipe to constrain one of the two or more etch characteristics and maintain the remainder of the two or more etch characteristics within defined bounds.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A method for modifying an integrated circuit design layout is presented and can include placing a plurality of target points in the proximity of a polygon representing a portion of the integrated circuit design; modifying the target point placement for some or all of the placed target points; fitting a curve to the target points; and redefining the portion of the integrated circuit as a contour defined by the fitted curve to modify the design layout. In some applications the modified design layout can be used as a target for an optical proximity correction algorithm or for other purposes.

Abstract: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Abstract: A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target points; (c) moving the etch target points according to a model of an etch process to produce a set of lithography-target points; and (d) synthesizing a photomask data set based on a model of a lithography process and the set of lithography-target points.

Abstract: This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.

Abstract: A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures to be measured and to obtain at least one computational model for optical proximity correction purposes.

Abstract: An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.