Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.

Abstract: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.

Abstract: Pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.

Abstract: First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction model is determined. An alignment feature can be used to align a measurement tool. In yet another embodiment, pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.

Abstract: Flare of an imaging system is measured using resist by employing the imaging system to directly expose a first part of the resist at an image plane of the imaging system to a first dose of radiation and to indirectly expose a second part of the resist as a result of flare. The imaging system exposes the second part of the resist to a second dose of radiation. Flare of the imaging system is determined from a pattern that is formed in the second part of the resist.

Abstract: A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.

Abstract: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Abstract: A system, method and program product that implement a design object that automatically provides compliance to alternating phase shifted mask (altPSM) rules are disclosed. The invention implements a design object that is used during layout to indicate a phase-shiftable design feature in the layout. Each design object includes a base shape indicative of the feature to be ultimately created and two different type phase shape identifiers that identify the requisite mask area and color of phase-shift required for that base shape. Each phase shape identifier is assigned to a portion of the base shape. During layout, overlapping placement of design objects is not allowed if the placement requires overlapping phase identifiers of the same type. Alternatively, placement is allowed where the phase identifiers of different type are separated by a minimum distance from each other defined by a buffer of the design object.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: The non-uniformity edge effect that can affect the quality of chips near the edge of a semiconductor wafer of various steps in the manufacture of integrated circuits is reduced. This is achieved by increasing the field area exposed by a step and repeat printer only when printing squares for chips located near the wafer edge. As a result there is also printed for processing an additional non-functional area outside the functional area to reduce the non-uniformity effect. This increases throughput of the printing apparatus.

Abstract: The non-uniformity edge effect that can affect the quality of chips near the edge of a semiconductor wafer of various steps in the manufacture of integrated circuits is reduced. This is achieved by increasing the field area exposed by a step and repeat printer only when printing squares for chips located near the wafer edge. As a result there is also printed for processing an additional non-functional area outside the functional area to reduce the non-uniformity effect. This increases throughput of the printing apparatus.

Abstract: A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.