Patents by Inventor Fred Session
Fred Session has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10749027Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.Type: GrantFiled: December 28, 2018Date of Patent: August 18, 2020Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
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Publication number: 20190245078Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.Type: ApplicationFiled: December 28, 2018Publication date: August 8, 2019Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
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Patent number: 9496391Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.Type: GrantFiled: March 11, 2014Date of Patent: November 15, 2016Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
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Publication number: 20140264569Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.Type: ApplicationFiled: March 11, 2014Publication date: September 18, 2014Applicant: Fairchild Semiconductor CorporationInventors: Joseph A. YEDINAK, Dean E. PROBST, Richard STOKES, Suku KIM, Jason HIGGS, Fred SESSION, Hui CHEN, Steven P. SAPP, Jayson PREECE, Mark L. Rinehimer
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Patent number: 8592277Abstract: A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.Type: GrantFiled: September 27, 2010Date of Patent: November 26, 2013Assignee: Fairchild Semiconductor CorporationInventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
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Patent number: 8450798Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the top surface of the semiconductor layer adjacent the trench so as to form a Schottky contact with the top surface of the semiconductor layer adjacent the trench. A surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.Type: GrantFiled: October 21, 2011Date of Patent: May 28, 2013Assignee: Fairchild Semiconductor CorporationInventor: Fred Session
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Publication number: 20120267714Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred Session
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Publication number: 20120098061Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Inventor: Fred Session
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Patent number: 8044461Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: GrantFiled: June 7, 2010Date of Patent: October 25, 2011Assignee: Fairchild Semiconductor CorporationInventor: Fred Session
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Publication number: 20110079845Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: ApplicationFiled: June 7, 2010Publication date: April 7, 2011Inventor: Fred Session
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Publication number: 20110014763Abstract: A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
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Patent number: 7807536Abstract: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.Type: GrantFiled: August 29, 2006Date of Patent: October 5, 2010Assignee: Fairchild Semiconductor CorporationInventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, Kent Naylor
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Patent number: 7732842Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: GrantFiled: May 11, 2007Date of Patent: June 8, 2010Assignee: Fairchild Semiconductor CorporationInventor: Fred Session
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Patent number: 7598144Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: GrantFiled: December 7, 2007Date of Patent: October 6, 2009Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Dean Probst, Fred Session
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Publication number: 20080135889Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: ApplicationFiled: May 11, 2007Publication date: June 12, 2008Inventor: Fred Session
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Patent number: 7385248Abstract: A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.Type: GrantFiled: August 9, 2005Date of Patent: June 10, 2008Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Dean Probst, Fred Session
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Publication number: 20080090339Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: ApplicationFiled: December 7, 2007Publication date: April 17, 2008Inventors: Robert Herrick, Dean Probst, Fred Session
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Publication number: 20070190728Abstract: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.Type: ApplicationFiled: August 29, 2006Publication date: August 16, 2007Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
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Publication number: 20070037327Abstract: A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: ApplicationFiled: August 9, 2005Publication date: February 15, 2007Inventors: Robert Herrick, Dean Probst, Fred Session