Method of forming low resistance gate for power MOSFET applications
A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
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This application is a continuation of U.S. application Ser. No. 11/467,997, filed Aug. 29, 2006, now U.S. Pat. No. 7,807,536, which claims the benefit of U.S. Provisional Application No. 60/772,315, filed Feb. 10, 2006, and is also related to the commonly assigned U.S. application Ser. No. 11/026,276, filed Dec. 29, 2004. All are incorporated herein by reference in their entirety for all purposes.
BACKGROUNDFast switching power transistors are needed to achieve voltage conversion at a minimum power loss. Low gate impedance is critical to achieving fast switching speeds and other performance parameters in such power devices as MOSFETs. However, as the devices are scaled down, the gate line-width gets narrower and the sheet resistance contribution to the equivalent series resistance (ESR) increases, adversely affecting the switching speed.
Conventionally, the gate dopant concentration is increased to minimize the gate resistance. However, current doping concentrations are at saturation levels and any higher levels can result in dopant penetration into the channel region depending on the gate oxide integrity and the thermal budget of the process. This coupled with the continued trend of shrinking cell pitch and diminishing cross sectional area of gate electrode has resulted in a significant increase in ESR as well as potential reliability issues.
Another challenge in design of power devices, in particular trench MOSFETs, has been forming reliable and low resistance contacts to source and well regions through source contact openings (sometimes formed by recessing silicon mesa) with increasingly high aspect ratios. The limitations of the manufacturing tools and the process technology, make it difficult to form reliable and low resistance contacts through high aspect ratio source contact openings.
Therefore, there is a need for new techniques for achieving reduced gate resistance and for forming reliable and low resistance contacts through high aspect ratio source contact openings.
BRIEF SUMMARYIn accordance with one embodiment of the invention, a trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
In accordance with another embodiment of the invention, a shielded gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, and then a shield dielectric lining lower sidewalls and bottom of the trench is formed. A lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric is formed over the shield electrode. A dielectric layer lining upper trench sidewalls and extending over mesa regions adjacent the trench is formed. A conductive seed layer is formed over the inter-electrode dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
In accordance with another embodiment of the invention, a trench gate field effect transistor is formed as follows. A trench is formed in a silicon region. A first dielectric layer is formed lining the trench sidewalls but being discontinuous along the trench bottom so that a surface of the silicon region along the trench bottom is exposed. A low resistance material is grown directly over the exposed surface of the silicon region, wherein the low resistance material is selective to the exposed silicon along the trench bottom. Oxygen is implanted into the trench to thereby form a second dielectric layer between the low resistance material and the exposed silicon region along the trench bottom, such that the low resistance material is completely insulated from the silicon region by the first and second dielectric layers.
In accordance with another embodiment of the invention, a trench gate field effect transistor is formed as follows. A trench is formed in a silicon region. A dielectric layer is formed lining the trench sidewalls and bottom and extending over surfaces of the silicon region adjacent the trench. A conductive layer is formed extending along trench sidewalls and bottom and over surfaces of the silicon region adjacent the trench such that horizontally extending portions of the conductive layer are thicker than its vertically extending portions. The vertically extending portions of the conductive layer are completely removed while horizontally extending portions of the conductive layer remain including a horizontally extending portion along the trench bottom forming a conductive seed layer. A low resistance material is grown directly over the conductive seed layer, the low resistance material being highly selective to the conductive seed layer.
In accordance with another embodiment of the invention, a shielded gate field effect transistor is formed as follows. Lower sidewalls and bottom of the trench are lined with shield dielectric. A lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric is formed over the shield electrode. A dielectric layer is formed lining upper trench sidewalls and extending over surfaces of the silicon region adjacent the trench. A conductive layer is formed extending along upper trench sidewalls and over the inter-electrode dielectric as well as the surfaces of the silicon region adjacent the trench such that horizontally extending portions of the conductive layer are thicker than its vertically extending portions. The vertically extending portions of the conductive layer are completely removed while horizontally extending portions of the conductive layer remain including a horizontally extending portion over the inter-electrode dielectric forming a conductive seed layer. A low resistance material is grown directly over the conductive seed layer, the low resistance material being highly selective to the conductive seed layer.
In accordance with another embodiment of the invention, a trench gate field effect transistor is formed as follows. A trench is formed in a silicon region. A dielectric layer lining the trench sidewalls and bottom is formed. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.
In accordance with another embodiment of the invention, a shielded gate field effect transistor is formed as follows. Lower sidewalls and bottom of the trench are lined with shield dielectric. A lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric is formed over the shield electrode. A dielectric layer is formed lining upper trench sidewalls and extending over surfaces of the silicon region adjacent the trench. A recessed polysilicon layer is formed in the trench over the inter-electrode dielectric. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.
In accordance with another embodiment of the invention, a trench gate field effect transistor includes a trench extending into a silicon region. A dielectric layer lines the trench sidewalls and bottom. A protective liner lines the trench sidewalls and bottom over the dielectric layer. A conductive seed layer is located in a bottom portion of the trench over the protective liner. A first layer of low resistance material extends over the conductive seed layer, wherein the protective liner protects the dielectric layer during processing steps carried out after forming the protective liner.
In accordance with another embodiment of the invention, a shielded gate field effect transistor includes a trench extending into a silicon region. A shield dielectric layer lines lower sidewalls and bottom of the trench. A shield electrode fills a lower portion of the trench. An inter-electrode dielectric extends over the shield electrode. A gate dielectric layer lines upper trench sidewalls. A protective liner lines the upper trench sidewalls over the gate dielectric layer, wherein the protective liner protects the dielectric layer during manufacturing process. A conductive seed layer recessed in the trench extends over the inter-electrode. A first layer of low resistance material extends over the conductive seed layer.
In accordance with another embodiment of the invention, a trench gate field effect transistor includes a trench extending into a silicon region. A dielectric layer lines the trench sidewalls and bottom. A conductive seed layer recessed in the trench extends over the dielectric layer. A layer of low resistance material extends over the conductive seed layer.
In accordance with another embodiment of the invention, a shielded gate field effect transistor includes a trench extending into a silicon region. A shield dielectric layer lines lower sidewalls and bottom of the trench. A shield electrode fills a lower portion of the trench. An inter-electrode dielectric layer extends over the shield electrode. A gate dielectric layer lines upper trench sidewalls. A conductive seed layer recessed in the trench extends over the inter-electrode dielectric layer. A layer of low resistance material extends over the conductive seed layer, the conductive seed layer and the layer of low resistance material forming part of a gate electrode in the trench.
In accordance with another embodiment of the invention, a trench gate field effect transistor includes a trench extending in a silicon region. A dielectric layer lines the trench sidewalls and bottom. A conductive seed layer lines trench sidewalls and bottom over the dielectric layer. A low resistance material at least partially fills the trench over the conductive seed layer.
In accordance with another embodiment of the invention, a shielded gate field effect transistor includes a trench extending in a silicon region. A shield dielectric layer lines lower sidewalls and bottom of the trench. A shield electrode fills a lower portion of the trench. An inter-electrode dielectric layer extends over the shield electrode. A gate dielectric layer lines upper trench sidewalls. A conductive seed layer lines upper trench sidewalls over the gate dielectric layer. A low resistance material at least partially fills the trench over the conductive seed layer.
In accordance with another embodiment of the invention, a field effect transistor is formed as follows. A plurality of trenches extending in a silicon region is formed. A dielectric layer lining sidewalls and bottom of each trench is formed. A recess is formed in the silicon region between every two adjacent trenches. A low resistance material is grown in each recess, wherein the low resistance material is selective to silicon such that the low resistance material grows from sidewalls of each recess inward and from bottom of each recess upward to thereby fill at least a portion of each recess.
In accordance with another embodiment of the invention, a field effect transistor is formed as follows. A plurality of trenches extending in a silicon region is formed. Lower sidewalls and bottom of each trench are lined with shield dielectric. A lower portion of each trench is formed with a shield electrode. An inter-electrode dielectric is formed over each shield electrode. A gate dielectric layer lines upper sidewalls of each trench. A gate electrode is formed in the trench over each inter-electrode dielectric. A recess is formed in the silicon region between every two adjacent trenches. A low resistance material is grown in each recess, wherein the low resistance material is selective to silicon such that the low resistance material grows from sidewalls of each recess inward and from bottom of each recess upward to thereby fill at least a portion of each recess.
A further understanding of the nature and the advantages of the invention disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.
In accordance with the present invention, various techniques for obtaining a low resistance gate in such devices a trench power MOSFETs with the flexibility to use a variety of low resistance materials and/or combinations thereof are described herein. Also, efficient methods for filling high aspect ratio features in devices are described.
Conductive materials with appropriate work function based on process integration and device requirement may be selected for conductive layer 108. In one embodiment, conductive materials with work function in the middle range of the energy band gap are used. Seed layer 108A may comprise polycrystalline or single crystalline silicon, metal or metal compound. In one embodiment, seed layer 108A is formed using the conventional methods utilized in forming n-doped or p-doped polysilicon gate electrodes in trench gate power devices. Use of polysilicon has the advantage of being compatible with existing process technologies. The polysilicon may be doped in-situ. In one embodiment, prior to forming seed layer 108A, a thick bottom dielectric (not shown) is formed along the bottom of the trench in order to minimize the gate to drain capacitance. In
In
In one embodiment, the low resistance material has an upper surface at a level substantially equal to the top surface of conventional recessed gates. In one embodiment, less than or equal to 80% of the gate electrode is made up of seed layer 108A, and the remaining portion of the gate electrode is made up of one or more low resistance material. In another embodiment, the low resistance material has a thickness greater than 400 Å. Forming such thick low resistance material is made possible by the selective deposition over a suitable seed layer.
In
Use of a conductive seed layer and an overlying low resistance material that is selective to the conductive seed layer is not limited to trench gate FETs. This technique may be similarly implemented in other types of power devices such as trench gate IGBTs and shielded gate MOSFETs and IGBTs. As an example, implementation of the seed layer technique in a shielded gate MOSFET is briefly described next with reference to
In
An alternate process sequence to that depicted by
Yet another alternate process sequence to that depicted by
In
In
In
The technique depicted by
A variation of the technique in
Similar to that described above in connection with dielectric layer 306 in the
Referring back to
In
In the embodiment where protective layer 514 comprises polysilicon and conductive layer 512B comprises a metal, conductive layer 512B is reacted such that it is completely consumed by polysilicon from both sides. The remainder of the structure (e.g., source regions, heavy body regions and source and drain interconnects) is formed using conventional processing techniques. As with the prior embodiments, the technique depicted by
In
A barrier layer 712, a second low resistance layer 714, and a cap layer 718 are sequentially formed over the first low resistance layer 710, as shown. In one embodiment, barrier layer 712 comprises titanium nitride and serves to prevent the two layers between which it lies from reacting together thus keeping their resistance low. A titanium nitride barrier layer 712 would also serve as an adhesion layer between layers 710 and 714. In another embodiment, the second low resistance layer 714 is eliminated so that cap layer is in contact with barrier layer 712. Cap layer 718 is from a highly conductive material to reduce the gate resistance. In one embodiment, cap layer 718 comprises one or more of tungsten, tantalum and molybdenum. In another embodiment, cap layer 718 comprises one or more salicidable material such as titanium (Ti), cobalt (Co), and Nickel (Ni).
Cap layer 718 also protects the underlying layers of the gate structures from contaminants during processing, and serves to contain the dopants in the underlying layers. In one embodiment, cap layer 718 comprises titanium silicide thus improving the temperature stability of the device (e.g., allow higher temperature processing). While the gate structure in
In
In an alternative variation of the
The various layers in each of trenches 700, 800, 900, 1000 and 1100 in respective
In
The technique in
Source contact aspect ratio continues to increase. The selective growth of low resistance material over a seed layer, in accordance with the present invention, allows for an excellent fill for the source contact with metal and/or silicides. Addition of enablers such as CMP can further add to the capabilities and would enable process optimization of the various techniques described herein.
The table below shows electrical properties of various candidates for the low resistance material in the above-described embodiments, and the corresponding equivalent series resistance (ESR) improvement. Depending on the design goals and performance targets, one or a combination of these materials may be used as the low resistance material in the various embodiments disclosed herein.
The improvements in ESR due to low resistance gate material would be more pronounced in devices and technologies with smaller gate cross-sectional area where the gate resistance is higher. The baseline used in the above calculations was N-type polysilicon at 3×1020/cm3 dopant concentration, and the following assumptions were made for the ESR improvement calculation. First, that ESR is dominated by gate resistance. Second, all the gate material is replaced, which may not be true for all the different gate stack combinations described above. Third, fifty percent of the gate area is filled with low resistance material.
In accordance with the present invention, the well known principle of selective deposition of low resistance materials such as refractory metals and their silicides, is used in combination with new techniques for forming a seed layer at the bottom of trenches or in high aspect ratio contact openings to reduce gate resistance and/or source resistance. Significant improvements in gate ESR (up to about 95%) can be achieved compared to conventional salicide processes. This is possible due to the increased thickness of the low resistance material made possible by the processes disclosed herein. The low gate resistance allows cell pitch reduction, resulting in significant improvements in the on resistance Rdson. In one embodiment, the potential for attack on a large area of the gate dielectric by the low resistance material is significantly reduced by using pre-reacted silicide rather than pure metal. This risk can be further reduced by using liners and spacers.
The various techniques disclosed herein require simple process in terms of integrating silicide layers with existing process flows. The materials used in the gate structure can be defined by the function such as, liner (metal or silicide gate), barrier (TiSi2 barrier or metal runner such as W), cap material (impurity and dopant out-diffusion), low resistivity gate material, seed material, and adhesion layer. These various layers may be combined in a number of different ways depending on the design goals. For example, a tungsten cap layer may be formed on top of polysilicon with TiSi2 as a barrier to the tungsten siliciding with the polysilicon.
The various process flows described herein are highly flexible in terms of the choice of low resistivity material and the gate material stack. Materials may include metals and metal silicides such as Al, W, WSi2, TiSi2 and potentially other refractory metals and their silicides (M-Si, M-Pt, Mo, Ta, Co, Ni). A dummy gate can be used when using a low melting point material such as aluminum. Also, a variety of materials and combinations, such as tungsten cap layer on top of polysilicon with TiSi2 as a barrier layer preventing the tungsten from siliciding with polysilicon, are possible.
Further, improved temperature stability is achieved as refractory materials such as W and their silicides are used. Also, capping an existing layer of TiSi2 for improving its thermal stability is possible. By properly selecting the type of silicide used, it is now possible to overcome any limitations due to critical dimension (CD) of the gate, along with the thermal stability.
A number of variations in terms of the amount of trench filled with polysilicon versus the low resistivity material are possible, including using almost no polysilicon to using all polysilicon with or without a capping material in high aspect ratio trenches.
The selective deposition process used in the various processes described herein fills the trench or source contact opening from bottom up and therefore fills effectively and consistently in spite of trench or source width variation. This variation center-edge may be caused during etch. By filling varying trenches from bottom up, this process minimizes reliability issues related to lack of good fill center to edge. Uniformity within the wafer, reliability and process consistency are thus improved.
While the various figures depicting particular process sequences show various layers/regions of the MOSFET being formed in a particular sequence, the invention is not limited as such. For example, the well region and source regions in the above embodiments may be formed at later or earlier stages of the process.
The various techniques described herein are not limited to the particular trench MOSFETs shown, but may be integrated directly or in modified form with other trench gate structures, trench structures with electrodes or silicon material therein, or shielded gate structures such as those shown in the above-referenced patent application Ser. No. 11/026,276, which disclosure is incorporate herein by reference in its entirety. Examples of devices in the above-referenced application with which the techniques of the present invention may be advantageously integrated can be found in
While the above provides a detailed description of various embodiments of the invention, many alternatives, modifications, and equivalents are possible. Also, it is to be understood that all numerical examples and material types provided herein to describe various dimensions, energy levels, doping concentrations, and different semiconducting or insulating layers are for illustrative purposes only and not intended to be limiting. For this and other reasons, therefore, the above description should not be taken as limiting the scope of the invention.
Claims
1. A method of forming a trench gate field effect transistor, the method comprising:
- forming a trench in a silicon region;
- forming a dielectric layer lining a sidewall of the trench and a bottom surface of the trench;
- forming a first polysilicon layer on the bottom surface of the trench;
- forming a first conductive material layer on an exposed surface of the first polysilicon layer;
- forming a second polysilicon layer on an exposed surface of the first conductive material layer; and
- performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the first conductive material layer to react.
2. The method of claim 1 further comprising:
- prior to performing the rapid thermal processing: forming a second conductive material layer on an exposed surface of the second polysilicon layer, the performing the rapid thermal processing further causes the second polysilicon layer and the second conductive material layer to react.
3. The method of claim 1 wherein the first conductive material layer includes at least one of tungsten, tantalum and molybdenum.
4. The method of claim 1 wherein forming the first conductive material layer includes depositing the first conductive material layer using directional deposition.
5. The method of claim 1 wherein the silicon region includes a substrate of a first conductivity type, the method further comprising:
- forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper portion of the silicon region;
- forming a well region of a second conductivity type in the epitaxial layer; and
- forming a source region of the first conductivity type in the well region and adjacent to the trench.
6. A method of forming a trench gate field effect transistor, the method comprising:
- forming a trench in a silicon region;
- forming a dielectric layer lining a sidewall of the trench and a bottom surface of the trench;
- forming a polysilicon layer on the bottom surface of the trench;
- forming a conductive material layer, the conductive material layer having a vertically extending portion on at least a portion of the dielectric layer lining the sidewall of the trench and a horizontally extending portion on an exposed surface of the polysilicon layer;
- removing the vertically extending portion of the conductive material layer while at least part of the horizontally extending portion of the conductive material remains,
- performing rapid thermal processing to cause the polysilicon layer and the conductive material layer to react.
7. The method of claim 6 wherein removing the vertically extending portions of the conductive material layer includes isotropically etching the conductive material layer.
8. The method of claim 6 wherein the conductive material layer includes a salicidable material.
9. The method of claim 6 wherein performing the rapid thermal processing causes a portion of the conductive material layer in contact with the polysilicon layer to react with the polysilicon layer, the method further comprising:
- removing un-reacted portions of the conductive material layer using a selective etch.
10. The method of claim 9 wherein the rapid thermal processing is a first rapid thermal processing, the method further comprising:
- after removing the un-reacted portions, performing a second rapid thermal processing to cause the reacted portion of the conductive material layer to change phase.
11. The method of claim 6 further comprising:
- forming a protective layer in the trench on an exposed surface of the horizontally extending portion of the conductive material layer that is extending over the polysilicon layer; and
- etching the conductive material layer to remove unprotected portions of the conductive material layer extending over surfaces of the silicon region, the unprotected portions not being covered by the protective layer.
12. A method of forming a shielded gate field effect transistor in a silicon trench, comprising:
- lining at least a lower portion of a sidewall of the trench and a bottom surface of the trench with a shield dielectric;
- depositing a shield electrode in at least a portion of the lower portion of the trench;
- forming an inter-electrode dielectric on an exposed surface of the shield electrode;
- forming a dielectric layer lining at least an upper portion of the sidewall of the trench and extending over a surface of a silicon region adjacent to the trench;
- forming a polysilicon layer in the trench on an exposed surface of the inter-electrode dielectric;
- forming a conductive material layer, the conductive material layer having a vertically extending portion on at least a portion of the dielectric layer lining the sidewall of the trench and a horizontally extending portion on an exposed surface of the polysilicon layer; and
- performing rapid thermal processing to cause the polysilicon layer and the conductive material layer to react.
13. The method of claim 12 further comprising:
- forming a protective layer on an exposed surface of the conductive material layer, the protective layer serving to prevent dopants in at least one underlying layer from diffusing out.
14. The method of claim 12 wherein the conductive material layer includes at least one of tungsten, tantalum and Moly (Mo).
15. The method of claim 12 wherein forming the conductive material layer includes depositing the conductive material layer using directional deposition.
16. The method of claim 12 further comprising:
- prior to performing rapid thermal processing, removing the vertically extending portion of the conductive material layer while at least part of the horizontally extending portion of the conductive material layer remains;
- forming a protective layer in the trench on an exposed surface of the horizontally extending portion of the conductive material layer on the polysilicon layer; and
- etching the conductive material layer to remove unprotected portions of the conductive material layer extending over a surfaces of the silicon region, the unprotected portions not being covered by the protective layer.
17. The method of claim 16 wherein removing the vertically extending portions includes isotropically etching the conductive material layer.
18. The method of claim 16 wherein the protective layer includes at least one of polysilicon and BPSG.
19. The method of claim 12 wherein the conductive material layer includes a salicidable material.
20. The method of claim 12 wherein the rapid thermal processing causes a portion of the conductive material layer in contact with the polysilicon layer to react with the polysilicon, the method further comprising:
- removing un-reacted portions of the conductive material layer using a selective etch.
21. The method of claim 20 wherein the rapid thermal processing is a first rapid thermal processing, the method further comprising:
- after removing the un-reacted portions, performing a second rapid thermal processing to cause the reacted portion of the conductive material layer to change phase.
22. The method of claim 12 wherein the silicon region includes a substrate of a first conductivity type, the method further comprising:
- forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper portion of the silicon region;
- forming a well region of a second conductivity type in the epitaxial layer; and
- forming a source region of the first conductivity type in the well region and adjacent to the trench.
23. A method of forming a trench gate field effect transistor, the method comprising:
- forming a trench in a silicon region;
- forming a dielectric layer lining a sidewall of the trench and a bottom surface of the trench;
- forming a polysilicon layer on the bottom surface of the trench;
- forming a conductive material layer on an exposed surface of the polysilicon layer;
- performing rapid thermal processing to cause the polysilicon layer and the conductive material layer to react;
- forming a protective layer in the trench on an exposed surface of a horizontally extending portion of the conductive material layer that is extending over the polysilicon layer; and
- etching the conductive material layer to remove unprotected portions of the conductive material layer extending over surfaces of the silicon region, the unprotected portions not being covered by the protective layer.
24. The method of claim 23 wherein the protective layer includes at least one of polysilicon and BPSG.
25. The method of claim 23 wherein the conductive material layer includes a salicidable material.
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Type: Grant
Filed: Sep 27, 2010
Date of Patent: Nov 26, 2013
Patent Publication Number: 20110014763
Assignee: Fairchild Semiconductor Corporation (South Portland, ME)
Inventors: Sreevatsa Sreekantham (Chandler, AZ), Ihsiu Ho (Salt Lake City, UT), Fred Session (Sandy, UT), James Kent Naylor (Kaysville, UT)
Primary Examiner: Mary Wilczewski
Assistant Examiner: Toniae Thomas
Application Number: 12/891,147
International Classification: H01L 21/336 (20060101);