Patents by Inventor Frederic Allibert

Frederic Allibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847370
    Abstract: A method for dissolving a buried oxide in a silicon-on-insulator wafer comprises providing a silicon-on-insulator wafer having a silicon layer attached to a carrier substrate via a buried oxide layer, and annealing the silicon-on-insulator wafer to at least partially dissolve the buried oxide layer. The method further comprises a step of providing an oxygen scavenging layer on or over the silicon layer before the annealing step.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 24, 2020
    Assignee: Soitec
    Inventor: Frederic Allibert
  • Patent number: 10819282
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Publication number: 20200169222
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Application
    Filed: May 23, 2018
    Publication date: May 28, 2020
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Publication number: 20200020520
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Application
    Filed: January 11, 2018
    Publication date: January 16, 2020
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Publication number: 20190259617
    Abstract: A method for dissolving a buried oxide in a silicon-on-insulator wafer comprises providing a silicon-on-insulator wafer having a silicon layer attached to a carrier substrate via a buried oxide layer, and annealing the silicon-on-insulator wafer to at least partially dissolve the buried oxide layer. The method further comprises a step of providing an oxygen scavenging layer on or over the silicon layer before the annealing step.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 22, 2019
    Inventor: Frederic Allibert
  • Patent number: 10002882
    Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 19, 2018
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Frederic Allibert, Christophe Maleville
  • Patent number: 9620626
    Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 11, 2017
    Assignees: SOITEC, STMICROELECTRONICS, INC.
    Inventors: Frédéric Allibert, Pierre Morin
  • Publication number: 20160372484
    Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 22, 2016
    Inventors: Bich-Yen Nguyen, Frederic Allibert, Christophe Maleville
  • Patent number: 9443933
    Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: September 13, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frédéric Allibert, Maud Vinet
  • Publication number: 20150325686
    Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicants: STMICROELECTRONICS, INC., SOITEC
    Inventors: Frédéric Allibert, Pierre Morin
  • Patent number: 9129800
    Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radio frequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate with an electrical resistivity of more than 500 Ohm.cm, (b) formation of a polycrystalline silicon layer on the substrate, the method comprising a step between steps a) and b) to form a dielectric material layer, different from a native oxide layer, on the substrate, between 0.5 and 10 nm thick.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 8, 2015
    Assignees: Soitec, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Frédéric Allibert, Julie Widiez
  • Publication number: 20150221723
    Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.
    Type: Application
    Filed: August 13, 2013
    Publication date: August 6, 2015
    Applicant: Commissariat à I'Energie Atomique et aux Energies Alternatives
    Inventors: Frédéric Allibert, Maud Vinet
  • Patent number: 9076713
    Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localized positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 7, 2015
    Assignees: Soitec, Commissariat à l'Énergie Atomique
    Inventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
  • Publication number: 20150168326
    Abstract: The invention relates to a method for testing a semiconductor substrate (1) for radiofrequency applications, characterized in that the electrical resistivity profile of the substrate as a function of depth, is measured and, using the profile, a criterion is calculated, defined by the formula (I): where D is the integration depth, ?(x) is the electrical conductivity measured at a depth x in the substrate, and L is a characteristic attenuation length of the electric field in the substrate. The invention also relates to a method for selecting a semiconductor substrate (1) for radiofrequency applications and to a device for implementing these methods.
    Type: Application
    Filed: January 15, 2013
    Publication date: June 18, 2015
    Applicant: SOITEC
    Inventor: Frederic Allibert
  • Publication number: 20140225182
    Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: Soitec
    Inventors: Mohamad A. Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8802539
    Abstract: The present invention relates to a process for preparing semiconductor-on-insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor-on-insulator type structure that includes such a trapping interface.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: August 12, 2014
    Assignee: Soitec
    Inventors: Frédéric Allibert, Sébastien Kerdiles
  • Patent number: 8765571
    Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Frederic Allibert
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Publication number: 20140084290
    Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate (1) with an electrical resistivity of more than 500 Ohm·cm, (b) formation of a polycrystalline silicon layer (4) on said substrate (1), said method comprising a step between steps a) and b) to form a dielectric material layer (5), different from a native oxide layer, on the substrate (1), between 0.5 and 10 nm thick.
    Type: Application
    Filed: March 22, 2012
    Publication date: March 27, 2014
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, Soitec
    Inventors: Frédéric Allibert, Julie Widiez
  • Publication number: 20140015023
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Soitec
    Inventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen