Abstract: Disclosed herein is a method comprised of providing a wafer comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, and a semiconducting layer positioned above the insulating layer, forming an opening in the semiconducting layer and the insulating layer to thereby expose a surface area of the bulk substrate, forming an alignment mark in the bulk substrate within the exposed surface area of the bulk substrate, and forming a layer of material above the alignment mark and in the opening. A wafer is also disclosed herein that is comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, a semiconducting layer positioned above the insulating layer, an opening formed in the semiconducting layer and the insulating layer, an alignment mark formed in the bulk substrate within an area defined by the opening, and a layer of material positioned above the alignment mark and within the opening.

Abstract: In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device.

Abstract: A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

Abstract: A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

Abstract: A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Abstract: A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter.

Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Abstract: The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.

Abstract: A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.

Abstract: A transistor, comprising a semiconducting substrate, a gate insulation layer positioned above the substrate, a gate electrode positioned above the gate insulation layer, a plurality of source/drain regions formed in the substrate, a first and a second sidewall spacer positioned adjacent the gate electrode, and a metal silicide layer formed above each of the source/drain regions, a portion of the metal silicide layer being positioned adjacent the first sidewall spacer and under the second sidewall spacer.

Abstract: The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or “t-shaped” gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon above the gate insulation layer, forming a layer of amorphous silicon above the layer of polysilicon, and patterning the layer of polysilicon and the layer of amorphous silicon to define a gate structure. The method further comprises reducing the width of the layer of polysilicon and the layer of amorphous silicon by performing an oxidation process, whereby the layer of polysilicon has a post-oxidation width that is less than the post-oxidation width of the layer of amorphous silicon, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode of the device.

Abstract: The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.

Abstract: A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

Abstract: Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.

Abstract: A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor.

Abstract: An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

Abstract: In manufacturing a semiconductor device, an etch stop layer is formed on a cobalt silicide layer during a heat treatment when the cobalt and silicon are transformed in a low resistance phase of cobalt silicide. During a predefined time period, oxygen is added to an inert gas ambient and leads to the formation of silicon oxide on the cobalt silicide. Thus, the present invention avoids a deposition step which would otherwise be necessary for forming the silicon oxide layer on top of the cobalt suicide.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.