Abstract: A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.

Abstract: A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.

Abstract: A method for measurement-based power and energy accounting for virtual machines distributed among at least one hosting device is disclosed.

Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.

Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.

Abstract: A method of managing power in a data processing system includes monitoring a system parameter indicative of power consumption. Responsive to determining that the parameter differs from a specified threshold, a system guest, such as an operating system, is forced to release a portion of its allocated system memory. The portion of system memory released by the guest is then reclaimed by the system. The reclaimed system memory and the resulting decrease in allocated memory may enable the system to reduce system memory power consumption. The operating system may de-allocate a portion of system memory when a balloon code device driver executing under the operating system requests the operating system to allocate memory to it. The system memory allocated to the balloon device driver is then reclaimed by supervisory code such as a hypervisor.

Abstract: A method of managing power in a data processing system includes monitoring a system parameter indicative of power consumption. Responsive to determining that the parameter differs from a specified threshold, a system guest, such as an operating system, is forced to release a portion of its allocated system memory. The portion of system memory released by the guest is then reclaimed by the system. The reclaimed system memory and the resulting decrease in allocated memory may enable the system to reduce system memory power consumption. The operating system may de-allocate a portion of system memory when a balloon code device driver executing under the operating system requests the operating system to allocate memory to it. The system memory allocated to the balloon device driver is then reclaimed by supervisory code such as a hypervisor.

Abstract: A system, apparatus and method for transmitting data on a private network in blocks of data without using TCP/IP as a protocol are provided. When data is to be transmitted on a private network, the data is divided into a plurality of packets and a MAC header is added to each packet. The header contains hardware addresses of the transmitting and receiving hosts as well as parameters of the data being transmitted. The hardware addresses are used to route the packets through the private network therefore obviating the use of TCP/IP to perform the same task. The data is ordinarily stored in contiguous sectors of a storage device; thus, ensuring that almost every packet will either contain data from a block of sectors or is a receipt acknowledgement of such packet.

Abstract: Processing system performance is improved while meeting power management constraints in a processing system by using activity factor headroom estimation. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.

Abstract: A method for measurement-based power and energy accounting for virtual machines distributed among at least one hosting device is disclosed.

Abstract: A processing system and computer program provides memory power management and memory failure management in large scale systems. Upon a decision to take a memory module off-line or place the module in an increased-latency state for power management, or upon a notification that a memory module has failed or been taken off-line or has had latency increased by another power management control mechanism, a hypervisor that supports multiple virtual machines checks the use of pages by each virtual machine and its guest operating system by using a reverse mapping. The hypervisor determines which virtual machines are using a particular machine memory page and may re-map the machine memory page to another available machine page, or may notify the virtual machines that the memory page has become or is becoming unavailable via a fault or other notification mechanism. Alternatively, or in the absence of a response from a virtual machine, the hypervisor can shut down the affected partition(s).

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.

Abstract: A system, apparatus and method for transmitting data on a private network in blocks of data without using TCP/IP as a protocol are provided. When data is to be transmitted on a private network, the data is divided into a plurality of packets and a MAC header is added to each packet. The header contains hardware addresses of the transmitting and receiving hosts as well as parameters of the data being transmitted. The hardware addresses are used to route the packets through the private network therefore obviating the use of TCP/IP to perform the same task. The data is ordinarily stored in contiguous sectors of a storage device; thus, ensuring that almost every packet will either contain data from a block of sectors or is a receipt acknowledgement of such packet.

Abstract: In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of time is required to reposition that physical element in response to each data write or read request. After selecting one or more data requests for dispatch based solely on an approaching or past due time deadline, additional requests are identified for data to be read or written to locations which are in close proximity to previously scheduled requests, previously selected additional requests, or the present position of the moveable physical element, obviating the need to expend the full amount of time required to accelerate the physical element and then decelerate the physical element to position it over the desired area within the information storage system. In this manner, data may be transferred to or retrieved from an information storage system more efficiently with less expenditure of time.

Abstract: A method and system for machine memory power and availability management in a processing system supporting multiple virtual machines provides a mechanism for supporting memory power management and memory failure management in large scale systems. Upon a decision to take a memory module off-line or place the module in an increased-latency state for power management, or upon a notification that a memory module has failed or been taken off-line or has had latency increased by another power management control mechanism, a hypervisor that supports multiple virtual machines checks the use of pages by each virtual machine and its guest operating system by using a reverse mapping. The hypervisor determines which virtual machines are using a particular machine memory page and may re-map the machine memory page to another available machine page, or may notify the virtual machines that the memory page has become or is becoming unavailable via a fault or other notification mechanism.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: One or more processors are activated and deactivated responsive to processing activity in order to meet a performance or response requirement. Hardware facilities or software modules monitor workload. A policy manager receiving workload information determines processor number based on a predetermined performance criteria. A resource pool module selects which processors are activated and deactivated in response to changes in the determined processor number as determined by the policy manager. The resource pool module prepares a selected processor for deactivation by migrating any processes or thread running thereon to other processor(s) in the pool of available processors and by flushing the contents of the selected processor's cache memory. A CPU power control module transitions a processor selected for deactivation from a full power state to a low-power state.

Abstract: A power-aware, logically partitioned data processing system and corresponding method of use include a set of physical resources and a hypervisor. The hypervisor creates partitions and allocates at least some of the physical resources to the partitions. The system further includes means for reducing the power consumption of any physical resources not allocated to a partition. The hypervisor may allocate physical resources to the partitions to maximize the number of unallocated physical resources. The physical resources may include processors and the hypervisor may allocate a fractional portion of at least one processor to a partition. In this embodiment, the system may reduce power consumption by scaling the supply voltage or clocking frequency to the fractionally allocated processor. The resources may include memory modules and the hypervisor may dynamically reduce the allocated memory and power consumption by minimizing the number of memory modules needed to support the memory allocated to the partitions.

Abstract: Disclosed is a server farm or MetaServer environment in which thin servers or server appliances each include a programmable network interface card providing logic required for implementing service processor functions. The combined implementation of the network interface and service processor hardware and software substantially eliminates redundancies, which previously existed when both were separate components. Service processor functions that are provided on the programmable network interface card includes gathering sensor data about the hardware, forwarding alerts regarding hardware state, initiating shutdown and restart on command, and responding to operating system service processor inquiries and commands. Additionally, other low-level management and control functions are provided on the programmable network interface card. Also, in one embodiment, a re-partitioning of the functions between the service processor (or probes) and the network interface is provided.