Patents by Inventor Freeman Leigh Rawson, III

Freeman Leigh Rawson, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6874036
    Abstract: A data processing network and an associated method of transmitting protocol data units (PDU) is disclosed. The network includes a first server including a first network interface card (NIC) that connects the first server to a central switch. The network further includes a second server including a second network interface card (NIC) that connects the second server to the central switch. The first NIC is configured to store a first PDU in a buffer upon determining that the first PDU is of a first type and to combine the first PDU stored in the buffer with a second PDU of a second type upon determining that the first and second PDU share a common target. The combined PDU is then forwarded to the common target as a single PDU thereby reducing the number of PDUs traversing the network.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: March 29, 2005
    Assignee: International Business Machines Corporation
    Inventor: Freeman Leigh Rawson, III
  • Patent number: 6857005
    Abstract: A data processing network in which console interactions are communicated to and from server appliances over the network. The system may include a server appliance configured to re-direct serial port transactions to a network port. The service appliance may include a mechanism for transmitting and receiving console data and control information via the network. The system further includes a console server for accepting and displaying console traffic that is sent over the network by a server appliance and for transmitting commands entered by a user back to the server appliance for processing.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: February 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Michael David Kistler, Freeman Leigh Rawson, III
  • Patent number: 6829637
    Abstract: A system comprising a cluster of diskless servers employing a distributed shared memory abstraction that presents an area of shared memory for two or more processes executing on different servers in the cluster. The invention provides the appearance of a shared memory space between two or more processes thereby potentially reducing disk latency or eliminating redundant computation associated with conventional server clusters. The DSM abstraction may be dynamically alterable such that selectable groups of processes executing on the cluster share a common address space temporarily. The shared memory spaces may be determined empirically or servers may subscribe to a group reactively in response to client requests. Multiple groups may exist simultaneously and a single server may belong to more than one group. The types of objects to which the abstraction is applied may be restricted. Shared memory may be restricted, for example, to read-only objects to alleviate consistency considerations.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ravindranath Kokku, Ramakrishnan Rajamony, Freeman Leigh Rawson, III
  • Patent number: 6823397
    Abstract: A method and system for determining liveness of targets within a metaserver environment utilizing programmable network interfaces. The network interface has access to the associated target computer's processor and memory. A memory location on the target is allocated to storing an internal liveness parameter. The parameter increases when the computer system is making forward progress or operating. The MetaServer stores an initial parameter value of the target when it activates the target. After a pre-selected period, the network interface of the target accesses the associated memory location and provides the current value of the parameter to the MetaServer. When the now value is larger than the previously stored value, the target is assumed to be live.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventor: Freeman Leigh Rawson, III
  • Patent number: 6766420
    Abstract: A data processing network, server device, and method in which an application program memory usage parameter is monitored where the parameter is indicative of the server device's performance and loading. If the memory usage parameter exceeds a specified criteria, the amount of the system memory available to the application program is reduced and a physical section of memory is deactivated to save power. The parameter may represent the server application's file cache hit rate and reducing the amount of memory available to the application program may include reducing the file cache size. Reducing the file cache size may include invalidating file cache data based upon a purge criteria that indicates when the data was most recently accessed. If the memory usage parameter falls below the specified criteria, additional system memory made be activated and made available to the application program to maintain performance at a desired level.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 20, 2004
    Assignee: International Business Machines Corporation
    Inventor: Freeman Leigh Rawson, III
  • Patent number: 6687756
    Abstract: A system and method for synchronizing a set of nodes connected to a central switch in a multi-node data processing system, such as a NUMA data processing system, are disclosed. Initially, time base register values are retrieved from each of the set of nodes. A common time base register value is then determined based upon the time base register values received from the nodes. The common time base register value that is determined is then broadcast to each of the nodes. Prior to reading the time base register values, packet traffic among the set of nodes may be halted by broadcasting a halt traffic packet to each of the nodes. In this embodiment, normal packet traffic may be resumed after synchronization by broadcasting a resume traffic packet to each of the nodes. The time base register values may be read by issuing a special purpose interrupt from a node adapter to one of the node processors in response to the adapter receiving a read time base packet from the switch.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corporation
    Inventor: Freeman Leigh Rawson, III
  • Patent number: 6601149
    Abstract: A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6502141
    Abstract: In a multi-node non-uniform memory access (NUMA) multi-processor system, a designated node synchronization processor on each node, is synchronized. Individual nodes accomplish internal synchronization of the other processors on each node utilizing well known techniques. Thus it is sufficient to synchronize one processor on each node. Node zero, a designated system node that acts as a synchronization manager, estimates the time it takes to transmit information in packet form to a particular, remote node in the system. As a result a time value is transmitted from the remote node to node zero. Node zero projects the current time on the remote node, based on the transmission time estimate and compares that with its own time and either updates its own clock to catch up with a leading remote node or sends a new time value to the other node, requiring the remote node to advance its time to catch up with that on node zero.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventor: Freeman Leigh Rawson, III
  • Patent number: 6499028
    Abstract: A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: December 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, David Brian Glasco, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6480966
    Abstract: A method, system, and computer readable medium for synchronizing performance monitors in the multiprocessor system are disclosed. The system includes a lead processor and at least one slave processor. The method includes informing the slave processor that a synchronization signal is forthcoming and waiting for an acknowledgment indicating that the slave processor is ready to receive the synchronization signal. In response to the slave processor's acknowledgment, the method includes sending the synchronization signal to the slave processor. The lead processor's performance monitors are set when the synchronization signal is sent and the slave processor's performance monitors are sent when the synchronization signal is received by the slave processor. In one embodiment, informing the slave processor that a synchronization signal is forthcoming is achieved by issuing a first inter-processor interrupt.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventor: Freeman-Leigh Rawson, III
  • Patent number: 6473085
    Abstract: A method and system for optimizing image quality while operating an interactive graphics application within a data processing system. First, the image rendering speed for each of the rendering modes available within the interactive graphics application are assessed. Upon initial operation of the interactive graphics system, a default rendering mode is activated. During operation of the interactive graphics application, the processing load imposed on the data processing system is monitored and utilized as a user activity metric. The active rendering mode is updated in accordance with the user activity metric, such that the speed of the selected rendering mode varies inversely with the current processing load.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazebllah Nabil Elinozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6442654
    Abstract: A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6349394
    Abstract: A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the system's physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, David Brian Glasco, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 5799188
    Abstract: A system and method for managing variable weight contexts in a multithreaded operating system. Each thread is allocated a standard thread state. In addition, each thread has an indicator of whether or not it has variable context in addition. The variable context indicator is used to access a flavor table that specifies the structure of the additional thread state information. The flavor table, in one embodiment, contains an indicator specifying whether the variable context data is to be saved and restored during a context switch. The standard thread state context is saved on a context and the variable context is saved only for those threads that use the context and only when the flavor table indicates that the variable context should be saved.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: August 25, 1998
    Assignee: International Business Machines Corporation
    Inventors: Ravindranath K. Manikundalam, Freeman Leigh Rawson, III
  • Patent number: 5794035
    Abstract: A system and method is provide for managing input/output (I/O) resources in a computer system. The system includes a hardware resource manager which tracks the use of the I/O resources. In addition, the hardware resource manager can allocate the resources between device drivers and provide a standard implementation to be used by device drivers.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: August 11, 1998
    Assignee: International Business Machines Corporation
    Inventors: David Barnett Golub, Freeman Leigh Rawson, III, Guy Gil Sotomayor, Jr.
  • Patent number: 5729710
    Abstract: A memory management method for a microkernel architecture and the microkernel itself feature template regions which are defined by the microkernel in the memory, as special objects. In the memory management method, after the microkernel is loaded into the memory of a data processing system, it begins creating task containers in the memory. It does this by forming template regions as special objects in the memory, the template regions having a set of attributes. Then, when the microkernel forms a task in the memory, it does so by mapping the template region into the task. The microkernel defines a virtual address space for the task based upon the template region. Later, when the microkernel conducts virtual memory operations on the template regions, the effect of the virtual memory operations is manifested in the task by means of the mapping relationship. In this manner, a single template region can be mapped into multiple tasks, simultaneously.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: March 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Michael Magee, Freeman Leigh Rawson, III, Guy Gil Sotomayor, Jr.