Abstract: A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.

Abstract: A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.

Abstract: A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90 nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90 nm in length.

Abstract: A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N? well, an oxide layer deposited on the N? well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

Abstract: Three-dimensional cross-point array and process flows. In an exemplary embodiment, a method is provided that includes forming stacked layers, performing a first lithography operation on the stacked layers to form cell columns, and performing a second lithography operation on the stacked layers to form first vertical openings that are filled with first conductor layers to form one or more word line connections in a first direction. The method also includes performing a third lithography operation on the stacked layers to form second vertical openings that are filled with second conductor layers to form one or more bit line connections in a second direction.

Abstract: Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a cell structure includes a word line, a selector layer, and a memory layer. The word line, the selector layer, and the memory layer form a vertical cell structure in which at least one of the selector layer and the memory layer are segmented to form a segment that blocks sneak path leakage current on the word line.

Abstract: A 3D array inside a substrate trench. In one aspect, an apparatus includes a substrate, a trench region in the substrate that is defined by a trench wall, and a 3D array having stacked word line layers formed in the trench region that follow a contour of the trench wall. In one aspect, a method includes forming a trench region in a substrate that has a top surface, the trench region is defined by a trench wall, and forming a 3D array having stacked word line layers in the trench region so that the stacked word line layers follow a contour of the trench wall and have exposed ends substantially at a level of the top surface.

Abstract: A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

Abstract: A three-dimensional double-density NAND flash memory device is disclosed. In one aspect, an apparatus includes a three dimensional stacked configuration of word line layers separated by insulating layers. The stacked configuration includes a selected number of the word line layers. The apparatus also includes an array of NAND strings deposited within the stacked configuration and perpendicular to a top surface of the stacked configuration. Each NAND string includes a charge-trapping layer that extends through the selected number of word line layers. The apparatus also includes one or more slits through the stacked configuration that divide each word line layer into a plurality of word line regions. The charge-trapping layer of each NAND string is coupled to two word line regions in each word line layer to form two charge-trapping regions to store two data bits in each word line layer.

Abstract: A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.

Abstract: A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90 nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90 nm in length.

Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

Abstract: A memory system able to store information using a hybrid volatile and nonvolatile memory device organized in a stacking configuration is disclosed. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.

Abstract: A method of storing information or data in a nonvolatile memory device with multiple-page programming is disclosed. The method, in one aspect, is able to activate a first drain select gate (“DSG”) signal. After loading the first data from a bit line (“BL”) to a nonvolatile memory page of a first memory block in response to activation of the first DSG signal during a first clock cycle, the first DSG signal is deactivated. Upon activating a second DSG signal, the second data is loaded from the BL to a nonvolatile memory page of a second memory block. The first data and the second data are simultaneously written to the first memory block and the second memory block, respectively.

Abstract: A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.

Abstract: A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

Abstract: A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.