Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a polyolefin-based polymer and an olefin-acrylate copolymer. The polyolefin-based polymer is represented by a formula (I): ?wherein R1 and R2 are selected from the group consisting of CH3, C2H5, and C3H7. The olefin-acrylate copolymer is represented by a formula (II): ?wherein R is selected from the group consisting of COOCH3, COOC2H5, and COOC4H9.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a fluoropolymer. The fluoropolymer has a plurality of spherulites, and the fractal dimension of each spherulite is lower than 12.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The first fluoropolymer has a first volume and a first melt flow index, and the second fluoropolymer has a second volume and a second melt flow index. The second melt flow index ranges from 0.4 g/10 min to 0.7 g/10 min and is lower than the first melt flow index, and a volume ratio by dividing the second volume by the first volume ranges from 0.4 to 0.6.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The first fluoropolymer includes a first melting point, and the second fluoropolymer has a second melting point lower than the first melting point. The difference between the first melting point and the second melting point is smaller than 14° C. The second fluoropolymer has a second melt flow index ranging from 0.4 g/10 min to 0.7 g/10 min.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The weight average molecular weight of the second fluoropolymer ranges from 630000 g/mol to 1100000 g/mol. The conductive filler is dispersed in the polymer matrix, thereby forming an electrically conductive path in the heat-sensitive layer.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

Abstract: A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.