Patents by Inventor Fu-Che Lee

Fu-Che Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11038014
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 15, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
  • Patent number: 11018005
    Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 11018141
    Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10971498
    Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 6, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Feng-Yi Chang
  • Publication number: 20210050353
    Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.
    Type: Application
    Filed: November 5, 2020
    Publication date: February 18, 2021
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Publication number: 20210043632
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 10861857
    Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10854613
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 10840182
    Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: November 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10825817
    Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 3, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • Patent number: 10825818
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 3, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10818664
    Abstract: A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 27, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10795255
    Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 6, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
  • Patent number: 10784265
    Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: September 22, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10784334
    Abstract: The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 22, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10777559
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
  • Publication number: 20200273862
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
    Type: Application
    Filed: March 22, 2019
    Publication date: August 27, 2020
    Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
  • Patent number: 10734284
    Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
  • Publication number: 20200227420
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Wen-Fu Huang, Fu-Che Lee
  • Patent number: 10714481
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: July 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee