Patents by Inventor Fu-Chen Chang
Fu-Chen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140782Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
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Patent number: 11967652Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: April 23, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Publication number: 20240074206Abstract: A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Chen CHANG, Kuo-Chi TU, Tzu-Yu CHEN, Sheng-Hung SHIH
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Publication number: 20240067816Abstract: A thermoplastic vulcanizate is provided. The thermoplastic vulcanizate includes: (A) about 100 parts by weight of a styrene copolymer rubber; (B) about 40-90 parts by weight of a thermoplastic elastomer; (C) about 5-15 parts by weight of an interfacial compatible resin; and (D) about 0.2-3 parts by weight of a cross-linking formulation, wherein the content of component (A) is greater than the content of component (B). Component (A) is dispersed in component (B) in the form of particles with a particle size of about 0.5-10 ?m.Type: ApplicationFiled: May 16, 2023Publication date: February 29, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jin-An WU, Fu-Ming CHIEN, Yun-Chen CHANG
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Publication number: 20240040800Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.Type: ApplicationFiled: January 5, 2023Publication date: February 1, 2024Inventors: Tzu-Yu Chen, Chu-Jie Huang, Wan-Chen Chen, Fu-Chen Chang, Sheng-Hung Shih, Kuo-Chi Tu
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Patent number: 11856788Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer.Type: GrantFiled: March 4, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yu Chen, Sheng-Hung Shih, Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Alexander Kalnitsky
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Patent number: 11849588Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.Type: GrantFiled: April 4, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Chen Chang, Kuo-Chi Tu, Tzu-Yu Chen, Sheng-Hung Shih
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Publication number: 20230389331Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a memory cell on the semiconductor substrate, where the memory cell includes a bottom contact, a memory material on the bottom contact, a top contact on the memory material, a first electrical isolation structure laterally surrounding the top contact, and a second electrical isolation structure laterally surrounding the memory material and the bottom contact.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Tzu-Yu Chen, Sheng-Hung Shih, Fu-Chen Chang, Kuo-Chi Tu
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Publication number: 20230371263Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
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Patent number: 11800720Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.Type: GrantFiled: November 17, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
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Publication number: 20230337440Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Fu-Chen Chang
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Publication number: 20230329001Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.Type: ApplicationFiled: March 28, 2022Publication date: October 12, 2023Inventors: Harry-Hak-Lay Chuang, Fu-Chen Chang, Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu
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Patent number: 11785777Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.Type: GrantFiled: January 12, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
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Publication number: 20230309318Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.Type: ApplicationFiled: May 26, 2023Publication date: September 28, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yu CHEN, Sheng-Hung SHIH, Fu-Chen CHANG, Kuo-Chi TU, Wen-Ting CHU
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Publication number: 20230274780Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu
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Publication number: 20230262991Abstract: The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: Fu-Chen Chang, Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu, Wen-Ting Chu
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Patent number: 11723213Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.Type: GrantFiled: July 15, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Fu-Chen Chang
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Patent number: 11706930Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.Type: GrantFiled: May 27, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Chen, Sheng-Hung Shih, Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
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Publication number: 20230217842Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Patent number: 11682456Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.Type: GrantFiled: August 28, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu