Patents by Inventor Fu-Chen Chang
Fu-Chen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11189788Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.Type: GrantFiled: April 26, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
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Patent number: 11183503Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.Type: GrantFiled: October 25, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
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Publication number: 20210343731Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Fu-Chen Chang
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Publication number: 20210233803Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
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Publication number: 20210202502Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Chen CHANG, Kuo-Chi TU, Tzu-Yu CHEN, Sheng-Hung SHIH
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Publication number: 20210184114Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.Type: ApplicationFiled: February 9, 2021Publication date: June 17, 2021Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Patent number: 11004728Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: GrantFiled: January 13, 2020Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Chun-Yen Lo, Kuo-Chio Liu
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Patent number: 10950784Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and has a lattice constant less than that of the active metal layer.Type: GrantFiled: June 7, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Publication number: 20210035992Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.Type: ApplicationFiled: October 25, 2019Publication date: February 4, 2021Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
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Publication number: 20210035993Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.Type: ApplicationFiled: February 3, 2020Publication date: February 4, 2021Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Fu-Chen Chang, Chih-Hsiang Chang, Sheng-Hung Shih
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Publication number: 20200388755Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.Type: ApplicationFiled: June 7, 2019Publication date: December 10, 2020Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Patent number: 10861761Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.Type: GrantFiled: February 21, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Shih-Yen Chen, Ruei-Yi Tsai, Pin-Yi Hsin
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Publication number: 20200350209Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Publication number: 20200343265Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
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Patent number: 10720360Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: December 9, 2016Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Publication number: 20200152506Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
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Publication number: 20200136040Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.Type: ApplicationFiled: April 26, 2019Publication date: April 30, 2020Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
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Patent number: 10535554Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: GrantFiled: October 5, 2017Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Chun-Yen Lo, Wen-Ming Chen, Kuo-Chio Liu
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Patent number: 10510605Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: July 24, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Publication number: 20190103389Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.Type: ApplicationFiled: February 21, 2018Publication date: April 4, 2019Inventors: FU-CHEN CHANG, CHENG-LIN HUANG, WEN-MING CHEN, SHIH-YEN CHEN, RUEI-YI TSAI, PIN-YI HSIN