Abstract: A semiconductor high pressure annealing device is described. The semiconductor high pressure annealing device includes a chamber body, a cover, a lifting mechanism, and a floating sealing structure. Air tightness between the chamber body and the cover is achieved by the floating sealing structure. A first sealing ring and a second sealing ring of the floating sealing structure are arranged on the top and the bottom for reducing the damage to the first sealing ring and the second sealing ring when the cover moves up and down. A preload spring assembly of the floating sealing structure can provide tension to assist in improving the air tightness between the chamber body and the cover.

Abstract: A dual-chamber pressure control method and a dual-chamber pressure control device are described. The dual-chamber pressure control method uses a stepped pressure adjustment to ensure that the pressure adjustment at each stage will not exceed a safe value of an internal chamber body. The dual-chamber pressure control device includes a dual-chamber member, an external chamber pressure control module, and an internal chamber pressure control module. The external chamber pressure control module is used to adjust an external chamber pressure of the dual-chamber member, such that an external chamber pressure value changes with time to show a stepped external chamber pressure adjustment line. The internal chamber pressure control module is used to adjust an internal chamber pressure of the dual-chamber member, such that an internal chamber pressure value changes with time to show a stepped internal chamber pressure adjustment line.

Abstract: A vertical dual-chamber annealing device is provided. The vertical dual-chamber annealing device includes an outer chamber unit, an inner chamber body, a temperature control unit, a supporting structure, and a gas-tight seal structure. The inner chamber body can be moved upward, such that the inner chamber body can be located in the outer chamber unit and supported by the supporting structure. After the supporting of the supporting structure is removed, the inner chamber body is moved downward and separated from the outer chamber unit. Therefore, an arrangement of the inner chamber body and the outer chamber unit can increase the convenience of cleaning and replacing the inner chamber body. The structure of the inner chamber body can enhance the uniformity of a reaction temperature. The gas-tight seal structure isolates an inert gas and a reactive gas, which is beneficial to the recovery and the reuse of the reactive gas.

Abstract: A locking mechanism is provided. The locking mechanism includes a base, a connecting rod, a fastener, and a linking member. The connecting rod and the fastener penetrate the base and are rotatable relative to the base. The connecting rod and the fastener are disposed parallel to each other. The linking member is connected to the connecting rod and the fastener, and is configured to link up the connecting rod and the fastener. Accordingly, the locking mechanism may be suitable for an expansion device with a specific size, and therefore the performance and the design flexibility of the electronic apparatus may be enhanced.

Abstract: A server apparatus includes a fixing mechanism and a holding casing having a fixing member. The fixing mechanism includes a containing casing having a guiding slot and an engaging hole, an actuator having a driving member and pivoted to the containing casing to be movable between a first position and a second position, and a driven structure. The driven structure has a driven member and a first slot and is slidable on the holding casing. When the engaging hole is engaged with the fixing member and the actuator moves to the first position, the driving member slides along the first slot to drive the driven structure to a mounting position, so as to slide the driven member along the guiding slot.

Abstract: A case module that is capable of installing a first electronic module and a second electronic module, includes a cage and a restraining component. The first electronic module can move relative to the cage to a first installation position along a first direction. The second electronic module can move relative to the cage to a second installation position along a second direction perpendicular to the first direction. When the first electronic module moves relative to the cage toward the first installation position along the first direction, the restraining component is driven to move relative to the cage toward a restraining position along the first direction. The second electronic module can be stopped by the restraining component when the restraining component is located at the restraining position.

Abstract: A case module that is capable of installing a first electronic module and a second electronic module, includes a cage and a restraining component. The first electronic module can move relative to the cage to a first installation position along a first direction. The second electronic module can move relative to the cage to a second installation position along a second direction perpendicular to the first direction. When the first electronic module moves relative to the cage toward the first installation position along the first direction, the restraining component is driven to move relative to the cage toward a restraining position along the first direction. The second electronic module can be stopped by the restraining component when the restraining component is located at the restraining position.

Abstract: A server apparatus includes a fixing mechanism and a holding casing having a fixing member. The fixing mechanism includes a containing casing having a guiding slot and an engaging hole, an actuator having a driving member and pivoted to the containing casing to be movable between a first position and a second position, and a driven structure. The driven structure has a driven member and a first slot and is slidable on the holding casing. When the engaging hole is engaged with the fixing member and the actuator moves to the first position, the driving member slides along the first slot to drive the driven structure to a mounting position, so as to slide the driven member along the guiding slot.

Abstract: An apparatus for throttling uplink data based on a temperature state is provided. The apparatus includes a temperature sensor, a processor and a memory. The temperature sensor senses an internal temperature of the apparatus. The memory is operatively coupled to the processor. The processor is configured to execute a program code stored in the memory to: compare the internal temperature to a corresponding temperature range according to a predetermined table of temperature ranges; and control a packet buffer to adjust a current data rate to a corresponding target data rate according to the comparison result.

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract: A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.

Abstract: A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.

Abstract: A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.

Abstract: An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.