Abstract: A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: A bus line termination circuit for limiting signal swing on a bus line to a reduced CMOS-swing. The termination circuit includes a switch and a first resistor connected in series between the bus line and a first voltage supply, and a second resistor connected in series between the bus line and a second voltage supply. The values of the first and second resistors are selected such that a termination voltage equal to the average of the first and second supply voltages exists on the bus line. The bus line is further connected to a receiver circuit having a threshold voltage equal to the average of the first and second supply voltages. The switch is controlled to disconnect the bus line from the first voltage supply when the bus line is in an inactive state. In an alternative embodiment, a termination circuit includes one or more voltage regulator circuits, each being coupled to the first and second voltage supplies. A clamping resistor coupled each voltage regulator circuit to the bus line.

Abstract: A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. The DRAM array is operated at a higher frequency than the frequency of the CPU bus clock signal, thereby reducing the access latency of the DRAM array. By operating the DRAM array at a higher frequency than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus.

Abstract: A computer unified memory architecture (UMA) system and method which includes a unified memory which is partitioned into a main memory and a main frame buffer memory, as well as a separate expansion frame buffer memory. Together, the main frame buffer memory and the expansion frame buffer memory form an entire frame buffer memory. The UMA system performs a display refresh operation by alternately accessing the main frame buffer memory and the expansion frame buffer memory. Because the display data bandwidth is split between the main frame buffer memory and the expansion frame buffer memory, the data bandwidth of the unified memory is effectively increased, thereby enabling higher system performance. The expansion frame buffer memory has a relatively small capacity, thereby retaining much of the cost benefit of a UMA system.

Abstract: A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device receives a stream of data values and a first clock signal from the memory system. The data values are sequentially read into the FIFO memory device in response to the first clock signal. The phase locked loop circuit receives a second clock signal, and in response generates an output clock signal which leads in phase the second clock signal. The output clock signal is provided to the FIFO memory device to cause the data values to be sequentially read from the FIFO memory device. As a result, a stream of data values is generated which is synchronized with the second clock signal.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A system for substrate scale integration by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor substrate so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: A pseudo nonvolatile memory cell which may be operated in a pseudo-nonvolatile mode is achieved by utilizing a thin direct tunneling dielectric adjacent to the charge retaining region in a traditional nonvolatile memory cell such as an EPROM, EEPROM, flash EPROM, or flash EEPROM cell. The use of the direct tunneling dielectric allows for greatly enhanced write/erase cycles (exceeding 100 gigacycles) and reduced data write/erase time (under 1 microsecond). The direct tunneling dielectric also results in a reduced data retention period. Consequently, refresh circuitry is provided to maintain the non-volatility of the memory cell. A back-up battery is used to power the refresh circuitry when the system power is removed. This mode of operation provides an effectively nonvolatile memory system that is suitable for replacing traditional nonvolatile memory devices.

Abstract: A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.

Abstract: A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: A high density, static random access memory (SRAM) circuit with single-ended memory cells employs a plurality of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells employs a single bit-line (BL) and two word lines.

Abstract: An integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 500.degree. C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of the said antifuse layer in excess of 500.degree. C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti.sub.5 Si.sub.3, TiSi, and/or TiSi.sub.2 than is yielded TiO, Ti.sub.2 O.sub.3, Ti.sub.3 O.sub.5, and/or TiO.sub.2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.

Abstract: A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.

Abstract: A technique for detecting whether electrical contact between a probe tip and a device under test ("DUT") has been established. A contact sensing circuit has a ground that is isolated from the ground of the DUT (and remaining portions of the test equipment) during contact sensing. The contact sensing circuit has elements that operate to apply a characteristic signal to one of the DUT terminals, such as its ground terminal. This causes virtually all the DUT circuit traces to track the applied signal (relative to the contact sensing ground). The contact sensing circuit further includes elements, coupled to the probe, that operate to detect the presence of the characteristic signal (relative to the contact sensing ground) on the probe. Once electrical contact has been established, the characteristic signal output is disconnected from the DUT, the test equipment ground is connected to the contact sensing circuit ground, and the probe output is coupled to the relevant portions of the test equipment circuitry.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.