Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

Abstract: A new lightly doped drain (LDD) process which does not required extra masking steps as compared to the conventional CMOS process is presented. By employing a new two layer side wall spacer technology, the LDD ion implantation for n-channel and p-channel devices can be carried out by sharing the n.sup.+ or p.sup.+ source and drain ion implantation mask. This approach provides maximum flexibility in designing optimum n.sup.- and p.sup.- channel LDD MOSFETs without using any additional mask steps other than the conventional CMOS mask levels. This process is also compatible with self-aligned silicide process.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.