Patents by Inventor Fu-Chih Yang

Fu-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Insulated gate bipolar transistor structure having low substrate leakage
    Patent number: 9379188
    Abstract: A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker-Hsiao Huo, Chih-Chang Cheng, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai, Ru-Yi Su
  • High voltage resistor with high voltage junction termination
    Patent number: 9373619
    Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    Publication number: 20160172475
    Abstract: A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 16, 2016
    Inventors: Po-Chih Chen, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu
  • HIGH VOLTAGE TRANSISTOR STRUCTURE
    Publication number: 20160155841
    Abstract: An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Embedded JFETs for High Voltage Applications
    Publication number: 20160141418
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Source tip optimization for high voltage transistor devices which includes a P-body extension region
    Patent number: 9331195
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage
    Publication number: 20160111498
    Abstract: A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 21, 2016
    Inventors: Ker-Hsiao Huo, Chih-Chang Cheng, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai
  • Strip-ground field plate
    Patent number: 9306012
    Abstract: Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ru-Yi Su, Po-Chih Chen, Ming-Cheng Lin, Fu-Chih Yang, Chun Lin Tsai
  • Stacked and tunable power fuse
    Patent number: 9299694
    Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
  • Bootstrap MOS for High Voltage Applications
    Publication number: 20160056303
    Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.
    Type: Application
    Filed: November 4, 2015
    Publication date: February 25, 2016
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker-Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20160049505
    Abstract: A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 18, 2016
    Inventors: King-Yuen WONG, Chen-Ju YU, Fu-Wei YAO, Chun-Wei HSU, Jiun-Lei Jerry YU, Chih-Wen HSIUNG, Fu-Chih YANG
  • Method of forming a semiconductor structure
    Patent number: 9263565
    Abstract: A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
  • Method of making an insulated gate bipolar transistor structure
    Patent number: 9257533
    Abstract: A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Embedded JFETs for high voltage applications
    Patent number: 9257979
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • PLASMA PROTECTION DIODE FOR A HEMT DEVICE
    Publication number: 20160027698
    Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
    Type: Application
    Filed: October 1, 2015
    Publication date: January 28, 2016
    Inventors: King-Yuen Wong, Chun-Wei Hsu, Chen-Ju Yu, Fu-Wei Yao, Jiun-Lei Jerry Yu, Fu-Chih Yang, Po-Chih Chen
  • HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME
    Publication number: 20160005823
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Fu-Wei YAO, Chun-Wei HSU, Chen-Ju YU, Jiun-Lei Jerry YU, Fu-Chih YANG, Chih-Wen HSIUNG, King-Yuen WONG
  • High electron mobility transistor and method of forming the same
    Patent number: 9224829
    Abstract: A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chen-Ju Yu, Fu-Wei Yao, Jiun-Lei Jerry Yu, Fu-Chih Yang, Po-Chih Chen, Chun-Wei Hsu
  • High voltage resistor
    Patent number: 9224827
    Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
  • Insulated gate bipolar transistor structure having low substrate leakage
    Patent number: 9214547
    Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • METHOD OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR
    Publication number: 20150349087
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Fu-Wei YAO, Chen-Ju YU, King-Yuen WONG, Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Chih YANG, Chun Lin TSAI