Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 µm. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 um. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 ?m. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

Abstract: A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 ?m. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

Abstract: A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.

Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom control gate lines, a plurality of bottom source lines, a stacked structure on the bottom source lines, a plurality of bit lines disposed on the stacked structure, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of stacked layers insulated from one another and respectively located at different levels. Each stacked layer includes a plurality of word lines. Each word line and the corresponding pillar structure, which is connected between the corresponding bit line and the corresponding bottom source line, define a memory cell. Each pillar structure includes an outermost ferroelectric layer, a conductive core gate column, and a surrounding channel layer disposed therebetween. The conductive core gate column is electrically connected to the corresponding bottom control gate line.

Abstract: A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.

Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

Abstract: A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer.

Abstract: A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer.

Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom control gate lines, a plurality of bottom source lines, a stacked structure on the bottom source lines, a plurality of bit lines disposed on the stacked structure, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of stacked layers insulated from one another and respectively located at different levels. Each stacked layer includes a plurality of word lines. Each word line and the corresponding pillar structure, which is connected between the corresponding bit line and the corresponding bottom source line, define a memory cell. Each pillar structure includes an outermost ferroelectric layer, a conductive core gate column, and a surrounding channel layer disposed therebetween. The conductive core gate column is electrically connected to the corresponding bottom control gate line.