Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom control gate lines, a plurality of bottom source lines, a stacked structure on the bottom source lines, a plurality of bit lines disposed on the stacked structure, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of stacked layers insulated from one another and respectively located at different levels. Each stacked layer includes a plurality of word lines. Each word line and the corresponding pillar structure, which is connected between the corresponding bit line and the corresponding bottom source line, define a memory cell. Each pillar structure includes an outermost ferroelectric layer, a conductive core gate column, and a surrounding channel layer disposed therebetween. The conductive core gate column is electrically connected to the corresponding bottom control gate line.

Abstract: A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.

Abstract: A ferroelectric field effect transistor is provided. Within the ferroelectric field effect transistor, a semiconductor substrate, a dielectric layer, a polarity retention layer and a conductive layer are sequentially fabricated. The polarity retention layer includes a ferroelectric layer and an anti-ferroelectric layer. By switching directions of electric dipoles in the ferroelectric layer, the operation speed of the memory including the ferroelectric field effect transistor is increased. A ferroelectric memory and a data writing method, a data reading method and a manufacturing method thereof are also provided.

Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

Abstract: A ferroelectric tunnel junction unit, a manufacturing method of a ferroelectric film thereof, a memory element, and a method of reading and writing the memory element are disclosed. The ferroelectric tunnel junction unit includes: a first electrode, a second electrode and a ferroelectric film sandwiched between the first and the second electrodes. The ferroelectric film includes at least a base substance and a number of dopants, the base substance including two oxides. Each oxide is at least one of an alkaline earth metal oxide and a transition metal oxide. The dopants include aluminum, silicon, titanium, tantalum, nitrogen, lanthanum, tantalum nitride, titanium nitride, or any combination thereof. By doping different dopants into the base substance of the ferroelectric film and adjusting the doping concentration of the dopants, a coercive electric field of the ferroelectric film may be tuned.

Abstract: A semiconductor light emitting device, such as the light emitting diode (LED) or the laser diode (LD), having a structure in which a light emitting area is a double heterostructure or a multi-layer quantum well structure. The light emitting area is formed on a substrate. Subsequently, an electrically conductive oxide layer as a transparent window layer to eliminate the crowding effect is formed on the light emitting area. The substrate layer consists of a GaAs substrate and a GaAsP layer to increasing the band gap energy of the substrate. The electrically conductive oxide layer is formed of AlZnO(x) material, having a lower electrical resistivity and a high transparency in the visible wavelength region. The window layer is formed using a physical vapor deposition or a metalorganic chemical vapor deposition.

Abstract: A light emitting diode includes a semiconductor substrate of a first conductivity type. A first electrode is formed on a part of the substrate. A reflection stack of the first conductivity type is formed on the substrate. An active layer is then formed on the reflection stack. An anti-reflection stack of a second conductivity type is grown on the active layer, and the anti-reflection stack consists of a plurality of layers, wherein each layer has a thickness of (m+1).lambda./2, where m is zero or a positive integer and .lambda. is a wavelength of radiation generated by the active layer. A window layer of the second conductivity type is formed on the anti-reflection stack. A second electrode is then formed on a part of the window layer.

Abstract: A structure of a semiconductor light emitting device includes a GaAs substrate, a GaAsP interface substrate, a first cladding layer, an active layer, and a second cladding layer. The GaAsP interface substrate layer is formed on the GaAs substrate, in addition, the GaAsP interface substrate layer formed on the substrate is of a thickness such that the upper surface of the GaAsP interface substrate layer adjacent to the substrate is composed of single crystal. The first cladding layer of a first conductivity is formed on the GaAsP interface substrate layer. The active layer is formed on the first cladding layer, from which the light is generated in the active layer. The second cladding layer of a second conductivity is formed on the active layer.