Abstract: A multi-channel power system and a method of controlling a phase shift of the same are provided. The multi-channel power system includes one or more first DC to DC converters and one or more second DC to DC converters. The first DC-DC converter outputs a first pulse width modulated signal having a first default frequency. When the first DC-DC converter receives a reference clock signal, it outputs the first pulse width modulated signal having a frequency that is the same as that of the reference clock signal. The first DC-DC converter outputs a phase-shifted clock signal having a preset phase shift relative to the first pulse width modulated signal. The second DC-DC converter outputs a second pulse width modulated signal having a second default frequency. The second DC-DC converter outputs the second pulse width modulated signal having the preset phase shift according to the phase shift clock signal.

Abstract: A phase shift control circuit for a multi-channel system including a pulse control circuit and a current matching circuit is provided. The pulse control circuit includes first to third transistors, a front operational amplifier, comparers, a current mirror circuit, clock switch circuits and pulse generating circuits. The front operational amplifier has two input terminals connected to a voltage divider circuit and an output terminal of the first transistor respectively, and an output terminal connected to control terminals of all the transistors. One input terminal of the comparer is connected to an output terminal of the third transistor, and another input terminal of the comparer is connected to the output terminal of the first transistor or a reference voltage source. The pulse generators are connected to the comparers and the clock switch circuits respectively. The current mirror circuit is connected to the current matching circuit.

Abstract: A power converting device and a method thereof are provided. The power converting device includes a filter circuit, a zero-crossing comparison circuit, a counting circuit, a logic circuit, an oscillation circuit, and a control circuit. The zero-crossing comparison circuit outputs a zero-crossing signal when an inductor current is equal to a zero current. The counting circuit counts a time interval between two consecutive time points at which the inductor currents are equal to the zero current in a low power mode. When the logic circuit determines that the time interval is greater than a first time threshold, the control circuit transmits a first oscillating signal to the filter circuit from the oscillation circuit; otherwise, it outputs a second oscillating signal; it outputs a pulse-skipping mode signal when the interval time is less than a second time threshold.

Abstract: A phase adjusting device provided includes a main delay circuit, a first converter, a second converter, a first buck circuit, and a second buck circuit. The main delay circuit receives an input clock signal to generate a main delay signal. The first converter receives the input clock signal to generate a first conversion signal. The second converter is coupled to the main delay circuit to receive the main delay signal and generate a second conversion signal. The first buck circuit is coupled to the first converter to receive the first conversion signal and generate a first buck voltage. The second buck circuit is coupled to the second converter to receive the second conversion signal and generate a second buck voltage. A first phase difference is formed between the main delay signal and the input clock signal.

Abstract: A dual voltage output device includes a charging circuit and a control circuit. The charging circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, an inductor, a first capacitor and a second capacitor. The control circuit controls the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch so that a DC voltage source charges the inductor and the inductor charges the first capacitor and the second capacitor individually or together. Therefore, the capacitor provides a first voltage, and the second capacitor provides a second voltage.

Abstract: An electronic apparatus is removed from a power supply apparatus and that can be certified by detecting a secondary-side transformer coil by a no-load detecting unit. The no-load detecting unit is configured to turn off an output switch unit and a power factor correction and pulse width modulation controller. An intermittent driving unit is configured to drive a start unit once a pre-determined time. The start unit is configured to drive the power factor correction and pulse width modulation controller. A load detecting unit is configured to detect that the electronic apparatus is connected to the power supply apparatus. The load detecting unit is configured to drive the intermittent driving unit. The intermittent driving unit is configured to drive the start unit. The start unit is configured to drive the power factor correction and pulse width modulation controller.

Abstract: An electronic apparatus is removed from a power supply apparatus and that can be certified by detecting a secondary-side transformer coil by a no-load detecting unit. The no-load detecting unit is configured to turn off an output switch unit and a power factor correction and pulse width modulation controller. An intermittent driving unit is configured to drive a start unit once a pre-determined time. The start unit is configured to drive the power factor correction and pulse width modulation controller. A load detecting unit is configured to detect that the electronic apparatus is connected to the power supply apparatus. The load detecting unit is configured to drive the intermittent driving unit. The intermittent driving unit is configured to drive the start unit. The start unit is configured to drive the power factor correction and pulse width modulation controller.

Abstract: A method of processing application security for uses in a platform-as-a-service layer (PAAS layer) includes steps as follows. First, an application program is scanned to find out a vulnerable code segment. Then, when the vulnerable code segment isn't fixed through a security process, a secure code segment is weaved into this unfixed vulnerable code segment, so as to ensure the security of the application program. Moreover, a system of processing application security is also disclosed in specification.

Abstract: A flyback converter system prevents a primary side switch and a secondary side switch from being turned on simultaneously through a controller. The controller includes a turning on switch module, a turning off switch module, and an enabling switch module. The turning on switch module is for turning on the secondary side switch. The turning off switch module switches off the secondary side switch according to the impedance of a load and the switch cycle of the secondary side switch. The enabling switch module enables the secondary side switch according to the impedance of the load.

Abstract: A flyback converter system prevents a primary side switch and a secondary side switch from being turned on simultaneously through a controller. The controller includes a turning on switch module, a turning off switch module, and an enabling switch module. The turning on switch module is for turning on the secondary side switch. The turning off switch module switches off the secondary side switch according to the impedance of a load and the switch cycle of the secondary side switch. The enabling switch module enables the secondary side switch according to the impedance of the load.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: A high frequency stripline-type power divider/combiner comprising a patterned metal layer having an input and two output strips, a dielectric substrate, and a resistive material layer interposed between the metal layer and substrate. A portion of the resistive material layer defines a resistive bridge that extends between and resistively interconnects the output strips, thereby acting as a resistive load for the cancellation of reflected power output signals. The patterned metal layer and resistive bridge are concurrently defined by standard photolithographic and etching techniques, thereby allowing the simple and accurate fabrication of an integral power divider/combiner.