Patents by Inventor Fu-Chun Huang

Fu-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20210240959
    Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui LIN, Chun-Ren Cheng, Jhubei Huang, Fu-Chun Huang
  • Publication number: 20210231603
    Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
  • Publication number: 20210193904
    Abstract: A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: YI HENG TSAI, FU-CHUN HUANG, CHING-HUI LIN, CHUN-REN CHENG
  • Publication number: 20210117636
    Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
  • Patent number: 10984211
    Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 20, 2021
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
  • Patent number: 10955379
    Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 23, 2021
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
  • Publication number: 20210078857
    Abstract: A hybrid ultrasonic transducer and a method of manufacturing the same are provided. A method of manufacturing a semiconductor device includes the forming of a first substrate and a second substrate. The forming of the first substrate includes: depositing a membrane stack over a first dielectric layer; forming a third electrode over the first dielectric layer; and depositing a second dielectric layer over the membrane stack and the third electrode. The forming of the second substrate includes: forming a redistribution layer (RDL) having a fourth electrode; and etching a first cavity on a surface of the RDL adjacent to the fourth electrode. The method further includes: forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: YI HENG TSAI, FU-CHUN HUANG, CHING-HUI LIN, CHUN-REN CHENG
  • Patent number: 10944041
    Abstract: A hybrid ultrasonic transducer and a method of manufacturing the same are provided. A method of manufacturing a semiconductor device includes the forming of a first substrate and a second substrate. The forming of the first substrate includes: depositing a membrane stack over a first dielectric layer; forming a third electrode over the first dielectric layer; and depositing a second dielectric layer over the membrane stack and the third electrode. The forming of the second substrate includes: forming a redistribution layer (RDL) having a fourth electrode; and etching a first cavity on a surface of the RDL adjacent to the fourth electrode. The method further includes: forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi Heng Tsai, Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng
  • Publication number: 20200350311
    Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
    Type: Application
    Filed: July 8, 2020
    Publication date: November 5, 2020
    Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
  • Patent number: 10756086
    Abstract: A method of manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. The second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
  • Publication number: 20200105996
    Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.
    Type: Application
    Filed: May 24, 2019
    Publication date: April 2, 2020
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
  • Publication number: 20200103369
    Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.
    Type: Application
    Filed: May 1, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
  • Publication number: 20200098517
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: March 26, 2020
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20200006469
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
    Type: Application
    Filed: May 13, 2019
    Publication date: January 2, 2020
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Patent number: 9975754
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Chun Huang, Li-Chen Yen, Tzu-Heng Wu, Yi-Heng Tsai, Chun-Ren Cheng
  • Patent number: 9844778
    Abstract: A testing module is provided. The testing module includes a carrier, a block member, and a sampling assembly. A flow path connects a storage chamber to a mixing chamber to guide the flow of a fluid. The block member is formed in the flow path to block the fluid from flowing from the storage chamber to the mixing chamber before the connection of the sampling assembly. When the sampling assembly which contains a test sample is connected to the carrier, the fluid mixes with the test sample and flows to the mixing chamber.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 19, 2017
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yi An Shih, Fu Chun Huang, Cheng Chang Lai
  • Publication number: 20170297901
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.
    Type: Application
    Filed: April 26, 2017
    Publication date: October 19, 2017
    Inventors: FU-CHUN HUANG, LI-CHEN YEN, TZU-HENG WU, YI-HENG TSAI, CHUN-REN CHENG
  • Patent number: 9656855
    Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a sensing structure disposed over the dielectric layer, a bonding structure disposed over the dielectric layer, a conductive layer covering the sensing structure, and a barrier layer disposed over the dielectric layer, the conductive layer and the bonding structure, wherein the conductive layer and the bonding structure are at least partially exposed from the barrier layer.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Chun Huang, Li-Chen Yen, Tzu-Heng Wu, Yi-Heng Tsai, Chun-Ren Cheng
  • Patent number: 9267785
    Abstract: A centrifugal analysis system includes a driving device, a carrying device, a number of cassettes, and an optical sensor device. The carrying device includes a tray disposed on the driving device, a number of limitation mechanisms disposed at the tray. The cassettes are detachably disposed at the tray and respectively and correspond to the limitation mechanisms. When the driving device drives the carrying device to rotate, the optical sensor circularly detects the cassettes in sequence.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: February 23, 2016
    Assignee: Lite-On Technology Corporation
    Inventors: Fu-Chun Huang, Cheng Chang Lai