Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A first well region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and under the trench. A first gate electrode having the second conductivity type is disposed in the trench, and a second gate electrode is disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. A method for forming the semiconductor device is also provided.

Abstract: A package includes a substrate and a plurality of light-emitting chips. The substrate has a top surface. The light-emitting chips are disposed on the top surface of the substrate, in which a sum of the vertical projection areas of the light-emitting chips on the top surface of the substrate is less than 5% of an area of the top surface of the substrate.

Abstract: A light emitting diode device includes a light emitting diode chip, a wavelength conversion layer including a bottom surface facing a top surface of the light emitting diode chip, and an interlayer having a first portion between the light emitting diode chip and a part of the bottom surface of the wavelength conversion layer, and a second portion extending from the first portion and connected between a remaining part of the bottom surface of the wavelength conversion layer and a side surface of the light emitting diode chip. The second portion has a side surface including a linear surface substantially aligning with a side surface of the wavelength conversion layer, and a curved surface having a first end connected to the linear surface and a second end connected to the side surface of the light emitting diode chip. The linear surface and the curved surface define a chamfer angle.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A display device includes a driving substrate, multiple light-emitting elements, first and second transparent substrates, multiple pixels, and a patterned light-absorbing layer. The light-emitting elements are disposed on the driving substrate and used to emit a light. The first transparent substrate is disposed over the driving substrate and the light-emitting elements and includes at least one groove. The pixels are disposed in the groove and include a first sub-pixel, a second sub-pixel, and a third sub-pixel respectively aligned with one of the light-emitting elements. The second transparent substrate covers the first transparent substrate and the pixels. The patterned light-absorbing layer is disposed on the second transparent substrate and includes multiple first openings respectively aligned with the first, second, and third sub-pixels.

Abstract: A display device includes a driving substrate, multiple light-emitting elements, first and second transparent substrates, multiple pixels, and a patterned light-absorbing layer. The light-emitting elements are disposed on the driving substrate and used to emit a light. The first transparent substrate is disposed over the driving substrate and the light-emitting elements and includes at least one groove. The pixels are disposed in the groove and include a first sub-pixel, a second sub-pixel, and a third sub-pixel respectively aligned with one of the light-emitting elements. The second transparent substrate covers the first transparent substrate and the pixels. The patterned light-absorbing layer is disposed on the second transparent substrate and includes multiple first openings respectively aligned with the first, second, and third sub-pixels.

Abstract: A light emitting diode device includes a light emitting diode chip, a wavelength conversion layer including a bottom surface facing a top surface of the light emitting diode chip, and an interlayer having a first portion between the light emitting diode chip and a part of the bottom surface of the wavelength conversion layer, and a second portion extending from the first portion and connected between a remaining part of the bottom surface of the wavelength conversion layer and a side surface of the light emitting diode chip. The second portion has a side surface including a linear surface substantially aligning with a side surface of the wavelength conversion layer, and a curved surface having a first end connected to the linear surface and a second end connected to the side surface of the light emitting diode chip. The linear surface and the curved surface define a chamfer angle.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

Abstract: A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.

Abstract: A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.

Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor.

Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.