Abstract: A data processing method includes: configuring a predetermined memory space to record information regarding valid data of a memory device, where the information is used to indicate data associated to which logical memory spaces of the memory device is valid; and updating the information according to commands received from a host device.

Abstract: A method of storage space management for a storage device comprising a controller and a memory, comprising: calculating, by the controller, an expectedly used capacity and an effective capacity of the memory, wherein the effective capacity has a negative correlation with a number of blocks marked as bad blocks among a plurality of blocks of the memory; when the effective capacity is less than or equal to the declared capacity, and a difference between the effective capacity and the expectedly used capacity is less than a predetermined threshold capacity, prohibiting, by the controller, programming to the memory; and when the effective capacity is less than or equal to the declared capacity and the difference of the effective capacity and the expectedly used capacity is not less than the predetermined threshold capacity, permitting, by the controller, programming to the memory.

Abstract: A light-emitting package structure includes a light transmissive adhesive layer, a substrate, and at least one light-emitting diode chip. The light transmissive adhesive layer includes a first surface and a second surface facing away from the first surface. The substrate is on the first surface of the light transmissive adhesive layer. The light-emitting diode chip is on the second surface of the light transmissive adhesive layer. The light transmissive adhesive layer has a first portion and a second portion on the second surface, the first portion surrounds the second portion, a vertical projection area of the second portion on the substrate at least entirely covers a vertical projection area of the light-emitting diode chip on the substrate, and a thickness of the second portion is smaller than or equal to a thickness of the first portion.

Abstract: A picking apparatus is configured to pick up a plurality of micro elements. The picking apparatus includes an elastic plate, a substrate, a temperature-controlled adhesive layer, at least one heating element and a power source. The elastic plate has a first surface and a second surface opposite to each other. The substrate is disposed on the first surface. The temperature-controlled adhesive layer is disposed on the second surface and configured to adhere the micro elements. The heating element is disposed between the second surface and the temperature-controlled adhesive layer. The power source is electrically connected with the heating element. A viscosity of the temperature-controlled adhesive layer varies with a temperature of the temperature-controlled adhesive layer.

Abstract: A display device includes a substrate, a plurality of white light-emitting units, and a color filter layer. The white light-emitting units are arranged on the substrate at intervals, and the white light-emitting units are chip scale package (CSP). The color filter layer is above the white light-emitting units. Each of the white light-emitting units includes a light-emitting diode chip and a wavelength conversion film. The wavelength conversion film directly covers a top surface and side surfaces of the light-emitting diode chip, and the wavelength conversion film converts light emitted by the light-emitting diode chip into white light.

Abstract: A picking apparatus is configured to pick up a plurality of micro elements. The picking apparatus includes a main body and a plurality of picking portions. The picking portions connect with and protrude from the main body. Each of the picking portions has a first surface. The first surfaces are away from the main body and configured to pick up the micro elements. The main body has a second surface at least partially located between the picking portions. Each of the first surfaces has a first viscosity. The second surface has a second viscosity. The second viscosity is less than the first viscosity.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A first well region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and under the trench. A first gate electrode having the second conductivity type is disposed in the trench, and a second gate electrode is disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. A method for forming the semiconductor device is also provided.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A first well region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and under the trench. A first gate electrode having the second conductivity type is disposed in the trench, and a second gate electrode is disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. A method for forming the semiconductor device is also provided.

Abstract: A package includes a substrate and a plurality of light-emitting chips. The substrate has a top surface. The light-emitting chips are disposed on the top surface of the substrate, in which a sum of the vertical projection areas of the light-emitting chips on the top surface of the substrate is less than 5% of an area of the top surface of the substrate.

Abstract: A light emitting diode device includes a light emitting diode chip, a wavelength conversion layer including a bottom surface facing a top surface of the light emitting diode chip, and an interlayer having a first portion between the light emitting diode chip and a part of the bottom surface of the wavelength conversion layer, and a second portion extending from the first portion and connected between a remaining part of the bottom surface of the wavelength conversion layer and a side surface of the light emitting diode chip. The second portion has a side surface including a linear surface substantially aligning with a side surface of the wavelength conversion layer, and a curved surface having a first end connected to the linear surface and a second end connected to the side surface of the light emitting diode chip. The linear surface and the curved surface define a chamfer angle.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A display device includes a driving substrate, multiple light-emitting elements, first and second transparent substrates, multiple pixels, and a patterned light-absorbing layer. The light-emitting elements are disposed on the driving substrate and used to emit a light. The first transparent substrate is disposed over the driving substrate and the light-emitting elements and includes at least one groove. The pixels are disposed in the groove and include a first sub-pixel, a second sub-pixel, and a third sub-pixel respectively aligned with one of the light-emitting elements. The second transparent substrate covers the first transparent substrate and the pixels. The patterned light-absorbing layer is disposed on the second transparent substrate and includes multiple first openings respectively aligned with the first, second, and third sub-pixels.

Abstract: A display device includes a driving substrate, multiple light-emitting elements, first and second transparent substrates, multiple pixels, and a patterned light-absorbing layer. The light-emitting elements are disposed on the driving substrate and used to emit a light. The first transparent substrate is disposed over the driving substrate and the light-emitting elements and includes at least one groove. The pixels are disposed in the groove and include a first sub-pixel, a second sub-pixel, and a third sub-pixel respectively aligned with one of the light-emitting elements. The second transparent substrate covers the first transparent substrate and the pixels. The patterned light-absorbing layer is disposed on the second transparent substrate and includes multiple first openings respectively aligned with the first, second, and third sub-pixels.

Abstract: A light emitting diode device includes a light emitting diode chip, a wavelength conversion layer including a bottom surface facing a top surface of the light emitting diode chip, and an interlayer having a first portion between the light emitting diode chip and a part of the bottom surface of the wavelength conversion layer, and a second portion extending from the first portion and connected between a remaining part of the bottom surface of the wavelength conversion layer and a side surface of the light emitting diode chip. The second portion has a side surface including a linear surface substantially aligning with a side surface of the wavelength conversion layer, and a curved surface having a first end connected to the linear surface and a second end connected to the side surface of the light emitting diode chip. The linear surface and the curved surface define a chamfer angle.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

Abstract: A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.