Patents by Inventor Fu-Huan TSAI
Fu-Huan TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190096881Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10157916Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: April 10, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10141429Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.Type: GrantFiled: May 15, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
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Publication number: 20180337173Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: Fu-Huan Tsai, Han-Min Tsai, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
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Publication number: 20180294261Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: April 10, 2017Publication date: October 11, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20180233522Abstract: A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
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Patent number: 9947701Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.Type: GrantFiled: February 9, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
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Publication number: 20170352660Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.Type: ApplicationFiled: August 23, 2017Publication date: December 7, 2017Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
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Publication number: 20170345855Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.Type: ApplicationFiled: February 9, 2017Publication date: November 30, 2017Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
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Publication number: 20170345821Abstract: A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.Type: ApplicationFiled: September 2, 2016Publication date: November 30, 2017Inventors: Shu Fang FU, Chi-Feng HUANG, Chia-Chung CHEN, Victor Chiang LIANG, Fu-Huan TSAI
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Publication number: 20170317073Abstract: Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a substrate and having channel, source, and drain regions. The method includes forming a well in the semiconductor layer to have a first dopant, and implanting a second dopant into the well. The first and second dopants are of opposite doping types. A first portion of the well has a higher concentration of the second dopant than the first dopant. A second portion of the well under the first portion has a higher concentration of the first dopant than the second dopant. The method further includes forming a gate stack over the channel region, and forming source and drain features in the source and drain regions. The first portion of the well electrically connects the source and drain features.Type: ApplicationFiled: December 29, 2016Publication date: November 2, 2017Inventors: Fu-Huan Tsai, Han-Min Tsai, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
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Patent number: 9761584Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.Type: GrantFiled: June 5, 2015Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
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Publication number: 20170250267Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
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Patent number: 9653542Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.Type: GrantFiled: October 23, 2013Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
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Publication number: 20160358911Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.Type: ApplicationFiled: June 5, 2015Publication date: December 8, 2016Inventors: Chia-Chung CHEN, Chi-Feng HUANG, Victor Chiang LIANG, Fu-Huan TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Han-Min TSAI, Hong-Lin CHU
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Publication number: 20160358912Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.Type: ApplicationFiled: June 5, 2015Publication date: December 8, 2016Inventors: Chia-Chung CHEN, Chi-Feng HUANG, Victor Chiang LIANG, Fu-Huan TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Han-Min TSAI, Hong-Lin CHU
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Patent number: 9337269Abstract: A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. The fins are doped to form source, drain and buried channel regions. A gate stack is formed over the buried channel regions. Contacts are formed to provide electrical contacts to the source/drain regions and the gate.Type: GrantFiled: February 11, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Huan Tsai, Chia-Chung Chen, Feng Yuan, Chi-Feng Huang, Victor Chiang Liang
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Publication number: 20150228725Abstract: A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. The fins are doped to form source, drain and buried channel regions. A gate stack is formed over the buried channel regions. Contacts are formed to provide electrical contacts to the source/drain regions and the gate.Type: ApplicationFiled: February 11, 2014Publication date: August 13, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Huan Tsai, Chia-Chung Chen, Feng Yuan, Chi-Feng Huang, Victor Chiang Liang
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Publication number: 20150108581Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chia-Chung CHEN, Fu-Huan TSAI, Feng YUAN