Patents by Inventor Fu-Jen Shih

Fu-Jen Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11070403
    Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: repeatedly adjust a parameter of an equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 20, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10848263
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 24, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10637509
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a de-emphasis adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 28, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10630425
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yu-Da Chen
  • Patent number: 10630424
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10545694
    Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a thermal sensor. The thermal sensor senses ambient temperature to obtain a sensed temperature and provides the sensed temperature to the processor. When the processor determines that the sensed temperature is higher than a high-temperature threshold, the processor adjusts a data transfer speed of the predetermined interface according to a data processing speed required by subsequent data to be read from or written to the data storage device.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 28, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Chia-Ching Huang
  • Patent number: 10452122
    Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yen-Hung Chen
  • Patent number: 10275163
    Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 30, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yen-Hung Chen
  • Patent number: 10248608
    Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 2, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Wen-Chi Chao
  • Publication number: 20190007168
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.
    Type: Application
    Filed: June 20, 2018
    Publication date: January 3, 2019
    Inventor: Fu-Jen SHIH
  • Publication number: 20190007169
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.
    Type: Application
    Filed: June 20, 2018
    Publication date: January 3, 2019
    Inventors: Fu-Jen SHIH, Yu-Da CHEN
  • Publication number: 20190007160
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
    Type: Application
    Filed: June 20, 2018
    Publication date: January 3, 2019
    Inventor: Fu-Jen SHIH
  • Publication number: 20190007167
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a de-emphasis adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.
    Type: Application
    Filed: June 20, 2018
    Publication date: January 3, 2019
    Inventor: Fu-Jen SHIH
  • Publication number: 20180275892
    Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.
    Type: Application
    Filed: January 11, 2018
    Publication date: September 27, 2018
    Inventors: Fu-Jen SHIH, Chia-Ching HUANG
  • Publication number: 20180203632
    Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a thermal sensor. The thermal sensor senses ambient temperature to obtain a sensed temperature and provides the sensed temperature to the processor. When the processor determines that the sensed temperature is higher than a high-temperature threshold, the processor adjusts a data transfer speed of the predetermined interface according to a data processing speed required by subsequent data to be read from or written to the data storage device.
    Type: Application
    Filed: December 22, 2017
    Publication date: July 19, 2018
    Inventors: Fu-Jen SHIH, Chia-Ching HUANG
  • Publication number: 20180181528
    Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 28, 2018
    Inventors: Fu-Jen SHIH, Wen-Chi CHAO
  • Publication number: 20180157417
    Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Application
    Filed: November 22, 2017
    Publication date: June 7, 2018
    Inventors: Fu-Jen SHIH, Yen-Hung CHEN
  • Publication number: 20180157309
    Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 7, 2018
    Inventors: Fu-Jen SHIH, Yen-Hung CHEN
  • Patent number: 8786512
    Abstract: A dual-polarized antenna includes a ground plane, an inverted-F conductor unit with an inverted-F plane, an inverted-L conductor unit with an inverted-L plane and a stretched ground conductor unit with a T-shaped plane. The inverted-F plane is vertically connected to the inverted-L plane, the T-shaped plane and the ground plane respectively, and the T-shaped plane is vertically connected with the ground plane. Therefore, the inverted-F plane, the inverted-L plane and the stretched ground conductor unit correspond to each side of the ground plane respectively to form a dual-polarized radiation field.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Cipherlab Co., Ltd.
    Inventors: Fu-Jen Shih, Kuo-Pin Hsu, Yi-Teng Hsiao
  • Publication number: 20130120215
    Abstract: A dual-polarized antenna includes a ground plane, an inverted-F conductor unit with an inverted-F plane, an inverted-L conductor unit with an inverted-L plane and a stretched ground conductor unit with a T-shaped plane. The inverted-F plane is vertically connected to the inverted-L plane, the T-shaped plane and the ground plane respectively, and the T-shaped plane is vertically connected with the ground plane. Therefore, the inverted-F plane, the inverted-L plane and the stretched ground conductor unit correspond to each side of the ground plane respectively to form a dual-polarized radiation field.
    Type: Application
    Filed: January 24, 2012
    Publication date: May 16, 2013
    Applicant: CIPHERLAB CO., LTD.
    Inventors: Fu-Jen SHIH, Kuo-Pin HSU, Yi-Teng HSIAO