Patents by Inventor Fu-Jier Fan

Fu-Jier Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371865
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The a semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate electrode adjacent to the plurality of first structures; and an insulating layer between the second protection structure and the gate electrode.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: JHU-MIN SONG, CHIEN-CHIH CHOU, KONG-BENG THEI, FU-JIER FAN
  • Patent number: 12100706
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Chien-Chih Chou, Kong-Beng Thei, Fu-Jier Fan
  • Publication number: 20230317656
    Abstract: A semiconductor device is provided. The semiconductor device includes a first die, a second die, a first through via, and a second through. The first die includes a first substrate, a first interconnection structure disposed on the first substrate, and a plurality of first bonding substructures over the first interconnect structure. The second die includes a second substrate, a second interconnect structure disposed on the second substrate, and a plurality of second bonding substructures over the second interconnect structure. The plurality of second bonding substructures are bonded to the plurality of first bonding substructures. The first through via and the second through via extend through the second substrate and to the second interconnect structure, wherein the first through via and the second through via are electrically disconnected to each other.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: JHU-MIN SONG, FU-JIER FAN, KONG-BENG THEI, ALEXANDER KALNITSKY, HSIAO-CHIN TUAN
  • Patent number: 11710712
    Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Fu-Jier Fan, Kong-Beng Thei, Alexander Kalnitsky, Hsiao-Chin Tuan
  • Patent number: 11705449
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 11646308
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 11569363
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Publication number: 20220367452
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: JHU-MIN SONG, CHIEN-CHIH CHOU, KONG-BENG THEI, FU-JIER FAN
  • Publication number: 20220359502
    Abstract: A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: YI-SHENG CHEN, KONG-BENG THEI, FU-JIER FAN, JUNG-HUI KAO, YI-HUAN CHEN, KAU-CHU LIN
  • Publication number: 20220352044
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate having an isolation ring extending in the direction substantially parallel to the surface of the substrate, an active region over the substrate and laterally enclosed by the isolation ring, a seal ring structure over the substrate, the seal ring structure laterally enclosing the active region and including at least a wiring layer and at least a via layer, and an encapsulant material laterally enclosing the seal ring structure.
    Type: Application
    Filed: April 22, 2021
    Publication date: November 3, 2022
    Inventors: FU-JIER FAN, ALEXANDER KALNITSKY, KONG-BENG THEI, JHU-MIN SONG
  • Publication number: 20220302108
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 11417649
    Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Sheng Chen, Kong-Beng Thei, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin
  • Patent number: 11410995
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Chien-Chih Chou, Kong-Beng Thei, Fu-Jier Fan
  • Publication number: 20220216169
    Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: JHU-MIN SONG, FU-JIER FAN, KONG-BENG THEI, ALEXANDER KALNITSKY, HSIAO-CHIN TUAN
  • Patent number: 11302691
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Publication number: 20210343707
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
    Type: Application
    Filed: July 8, 2021
    Publication date: November 4, 2021
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Publication number: 20210280577
    Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
  • Patent number: 11063038
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Publication number: 20210193813
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Patent number: 11004844
    Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen