Recessed STI as the Gate Dielectric of HV Device
A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
This application is a continuation of U.S. patent application Ser. No. 16/045,252, entitled “Recessed STI as the Gate Dielectric of HV Device,” filed on Jul. 25, 2018, which is a divisional of U.S. patent application Ser. No. 15/061,709, entitled “Recessed STI as the Gate Dielectric of HV Device,” filed on Mar. 4, 2016, now U.S. Pat. No. 10,916,542 issued Feb. 9, 2021, which claims the benefit of U.S. Provisional Application No. 62/272,854, entitled “Recessed STI as the Gate Dielectric of HV Device,” filed on Dec. 30, 2015, which applications are hereby incorporated herein by reference.
BACKGROUNDHigh-Voltage Metal-Oxide-Semiconductor (HVMOS) devices are widely used in many electrical devices, such as Central Processing Unit (CPU) power supplies, power management systems, AC/DC converters, etc.
HVMOS devices have different structures than Medium-Voltage Metal-Oxide-Semiconductor (MVMOS) devices and Low-Voltage Metal-Oxide-Semiconductor (LVMOS) devices. In order to sustain high voltages applied between the gate and the drain of a HVMOS device, the gate dielectric of the HVMOS device is thicker than a gate dielectric of a MVMOS device and a gate dielectric of a LVMOS device. In addition, the doping concentrations of high-voltage well-regions are lower than that of the well regions of MVMOS devices and LVMOS devices in order to sustain higher gate-drain voltage.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A High-Voltage (HV) Metal-Oxide-Semiconductor (MOS) device and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the HV MOS device are illustrated. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Semiconductor substrate 20 includes a first portion in device region 100 and a second portion in device region 200. Device region 100 is a HV device region in which HV MOS device 186 (
Referring to
Next, as shown in
After the formation of the liner oxide, the remaining portions of trenches 32 are filled with another dielectric material. In accordance with some embodiments of the present disclosure, the filling material includes silicon oxide, and other dielectric materials such as SiN, SiC, SiON, or the like, may also be used. The filling dielectric material may be filled using High Aspect Ratio Process (HARP), High Density Plasma Chemical Vapor Deposition (HDP), SACVD, Atmospheric Pressure Chemical Vapor Deposition (APCVD), or the like.
Next, a steam anneal may be performed. The steam anneal may include annealing the structure shown in
A planarization such as Chemical Mechanical Polish (CMP) is then performed to remove excess portions of dielectric material 34 over the top surface of mask layer 24, resulting in the structure shown in
In subsequent steps, mask layer 24 and pad layer 22 are removed, followed by some cleaning processes, and the resulting structure is shown in
Next, as shown in
Next, as shown in
In a subsequent step, as shown in
Referring to
The remaining bottom portion 36B of STI region 36 has thickness T2. The remaining upper portions 36A of STI region 36 have thickness T1. The etching process may be adjusted to adjust the endurable voltage and the saturation current of the resulting HV MOS device. Depth D2 of recess 58 may be in the range between about 500 Å and about 1,400 Å in accordance with some embodiments. The optimal depth D2 is affected by various factors such as the thickness of gate dielectric 276 (
Next, referring to
Gate spacers 162 and 262 are formed on the sidewalls of gate stacks 160 and 260, respectively. The respective step is also shown as step 312 in the process flow shown in
Referring to
In addition, pickup regions 171, which are of p-type, are formed at the surface of HVPW regions 42 through an additional implantation step. P-type pickup regions 171 may also have a p-type impurity concentration between about 1019/cm3 and about 1021/cm3, and are referred to as P+ regions.
Referring to
Gate dielectrics 176 and 276 may include a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, or the like. Gate electrodes 178 and 278 may include conductive diffusion barrier layers formed of TiN, TaN, or the like. Gate electrodes 178 and 278 also include conductive layers such as metal-containing layers over the conductive diffusion barrier layers, wherein the metal-containing layers may be formed of cobalt, aluminum, or multi-layers thereof. The formation methods include PVD, CVD, or the like. A planarization step (for example, a CMP) is then performed to remove excess portions of the gate dielectrics and gate electrodes, leaving the structure in
In the embodiments illustrated in
Referring to
MOS device 186 is a HV MOS device. MOS device 286 is a MV MOS device or a LV MOS device, wherein the thickness of gate dielectric 276 (and 176) is selected to suit to the operation voltage levels of MOS device 286. The gate dielectric of HV MOS device 186 includes the remaining portion of STI region 36, which is thick enough to sustain the high voltage. In addition, gate dielectric 176 may also be formed as a part of the gate dielectric of HV MOS device 186. MV/LV MOS device 286 has gate dielectric 276, which is thinner than the thickness of gate dielectric 36. In addition, gate dielectrics 176 and 276 may be formed in a same formation process, and thus have a same thickness, and are formed of a same dielectric material.
The embodiments of the present disclosure have some advantageous features. It is desirable to make HV MOS devices and LV/MV devices to share the processes for forming replacement gates in order to reduce manufacturing cost. However, HV MOS devices have thick gate dielectrics, and hence the top surfaces of the gate dielectrics of HV MOS devices may be at substantially the same level as, or even higher than, the top surfaces of the dummy gate electrodes of the LV/MV MOS devices. As a result, the planarization for exposing the dummy gate electrodes of the LV/MV MOS devices may result in the full removal of the dummy gate electrodes of the HV MOS devices. This means replacement gates are unable to be formed for HV MOS devices by sharing the same process for forming replacement gates for LV/MV MOS devices. By recessing STI regions and forming the gate electrodes of the HV MOS devices in the recesses, the height difference between the top surfaces of the HV MOS device and LV/MV MOS devices is reduced, and the planarization may be performed without causing the full removal of the dummy gate electrodes of HV MOS devices. In addition, in accordance with the embodiments of the present disclosure, the STI regions are used as the gate dielectrics of the HV MOS devices, and hence the production cost is reduced.
In accordance with some embodiments of the present disclosure, a method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a MOS device.
In accordance with some embodiments of the present disclosure, a method includes forming a first and a second STI region extending from a top surface of a semiconductor substrate into the semiconductor substrate, and etching the first STI region to form a recess extending from a top surface of the first STI region into the first STI region. The first STI region includes a lower portion underlying the recess. The method further includes forming a first gate stack overlapping the lower portion of the first STI region, forming a second gate stack over and contacting a top surface of the semiconductor substrate, forming first source/drain regions on opposite sides of the first gate stack, and forming second source/drain regions on opposite sides of the second gate stack. One of the second source/drain regions contacts a sidewall of the second STI region. An ILD is formed over the first source/drain regions and the second source/drain regions. A planarization is performed to make a top surface of the first gate stack to be coplanar with a top surface of the second gate stack.
In accordance with some embodiments of the present disclosure, an integrated circuit structure includes a semiconductor substrate. An HVMOS device includes a gate dielectric having a portion lower than a top surface of the semiconductor substrate. A gate electrode is over the gate dielectric, wherein the gate electrode has a portion lower than the top surface of the semiconductor substrate. A source region and a drain region are on opposite sides of the gate dielectric.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A device comprising:
- a semiconductor substrate;
- an isolation region extending into the semiconductor substrate, wherein the isolation region comprises: a first bottom portion having a first top surface; first sidewall portions higher than the first top surface, wherein the first sidewall portions are connected to opposing ends of the first bottom portion;
- a gate dielectric having an U-shape in a cross-sectional view of the device, the gate dielectric comprising: a second bottom portion over and contacting the first top surface; and second sidewall portions over and connecting to opposing ends of the second bottom portion;
- a first well region; and
- a second well region, wherein the first well region and the second well region extend to opposite sides of the isolation region, and wherein both of the first well region and the second well region contact the first bottom portion and the first sidewall portions of the isolation region.
2. The device of claim 1, wherein the second bottom portion is substantially planar.
3. The device of claim 1 further comprising a gate spacer contacting the gate dielectric, wherein the gate spacer extends lower than a top surface of one of the first sidewall portions.
4. The device of claim 3, wherein the gate spacer is between, and is spaced apart from, the first sidewall portions of the isolation region.
5. The device of claim 1 further comprising a contact etch stop layer (CESL), wherein the CESL extends into a space between the gate dielectric and one of the first sidewall portions, and extends lower than a top surface of the one of the first sidewall portions.
6. The device of claim 5 further comprising an inter-layer dielectric over the CESL, wherein the inter-layer dielectric extends into the space, and extends lower than the top surface of the one of the first sidewall portions.
7. The device of claim 1 further comprising:
- a first High Voltage Well (HVW) region of a first conductivity type, wherein the first HVW region comprises a portion directly underlying the gate dielectric; and
- a second HVW region and a third HVW region on opposing sides of, and joining to, the first HVW region, wherein the second HVW region and a third HVW region contact sidewalls of the first sidewall portions of the isolation region.
8. The device of claim 7, wherein first HVW region extends laterally beyond, and is wider than, the gate dielectric.
9. The device of claim 1, wherein an entirety of the second bottom portion of the gate dielectric is lower than top ends of the first sidewall portions of the isolation region.
10. The device of claim 1 further comprising a transistor, wherein the transistor comprises an additional gate dielectric higher than top edges of the first sidewall portions of the isolation region.
11. A device comprising:
- a semiconductor substrate;
- an isolation region comprising edge portions and a middle portion between the edge portions, wherein the middle portion is recessed lower than the edge portions to form a recess;
- a gate stack extending into the recess;
- a gate spacer on a sidewall of the gate stack, wherein the gate spacer extends into the recess; and
- a first source/drain region and a second source/drain region extending into the semiconductor substrate, wherein the first source/drain region and the second source/drain region are on opposite sides of the isolation region.
12. The device of claim 11, wherein a top surface of the middle portion of the isolation region is lower than a top surface of the semiconductor substrate.
13. The device of claim 11, wherein the gate stack comprises a gate dielectric having a U-shape in a cross-sectional view of the device, wherein the U-shape comprises a bottom part, and two sidewall parts connecting to opposite ends of the bottom part, and wherein an entirety of the bottom part is in the recess.
14. The device of claim 11, wherein the gate spacer is between, and is laterally spaced apart from both of, the edges portions of the isolation region.
15. The device of claim 11 further comprising a contact etch stop layer, wherein the contact etch stop layer comprises a portion inside the recess.
16. The device of claim 15 further comprising an inter-layer dielectric over the contact etch stop layer, wherein the inter-layer dielectric further extends into the recess.
17. A device comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type in the semiconductor substrate;
- a second well region and a third well region on opposing sides of the first well region and in the semiconductor substrate, wherein the second well region and the third well region are of a second conductivity type opposite to the first conductivity type;
- an isolation region extending into the first well region, the second well region, and the third well region; and
- a transistor comprising: a gate stack; gate spacers on opposing sides of the gate stack, wherein both of the gate stack and the gate spacers extend into the isolation region; a first source/drain region in the second well region; and a second source/drain region in the third well region, wherein the first source/drain region and the second source/drain region are on opposite sides of, and are spaced apart from, the isolation region.
18. The device of claim 17, wherein the isolation region comprises:
- a bottom part; and
- a first sidewall part and a second sidewall part over and connected to the bottom part, wherein the gate spacers are between, and are separated from, the first sidewall part and the second sidewall part.
19. The device of claim 17 further comprising an additional isolation region in the semiconductor substrate, wherein the additional isolation region has a substantially planar top surface, and a sidewall of the additional isolation region contacts the first source/drain region.
20. The device of claim 17 further comprising a dielectric layer extending into the isolation region, wherein the dielectric layer contacts the gate spacers.
Type: Application
Filed: May 10, 2021
Publication Date: Sep 9, 2021
Inventors: Yi-Huan Chen (Hsinchu), Kong-Beng Thei (Pao-Shan Village), Fu-Jier Fan (Hsinchu), Ker-Hsiao Huo (Zhubei City), Kau-Chu Lin (Taichung City), Li-Hsuan Yeh (New Taipei City), Szu-Hsien Liu (Zhubei City), Yi-Sheng Chen (Hsinchu)
Application Number: 17/316,155